LTC3867_15 Datasheet, PDF (28/36 Pages) Linear Technology – Low IQ, Dual 2-Phase Synchronous Step-Down Controller

LTC3867
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3867 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. There is a precision 20µA current flowing
out of the FREQ pin. This allows the user to use a single
resistor to SGND to set the switching frequency when
no external clock is applied to the MODE/PLLIN pin. The
internal switch between the FREQ pin and the integrated
PLL filter network is on, allowing the filter network to be
pre-charged at the same voltage as of the FREQ pin. The
relationship between the voltage on the FREQ pin and
operating frequency is shown in Figure 14 and specified
in the Electrical Characteristics table. If an external clock
is detected on the MODE/PLLIN pin, the internal switch
mentioned above turns off and isolates the influence of the
FREQ pin. Note that the LTC3867 can only be synchronized
to an external clock whose frequency is within range of
the LTC3867’s internal VCO. A simplified block diagram
is shown in Figure 15.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f_OSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than f_OSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor C_LP holds the voltage.
1300
1100
900
700
500
300
100
0.4 0.6
0.8 1.0 1.2 1.4
V_FREQ (V)
1.6 1.8
3867 F14
Figure 14. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
2.4V 5V
20µA
R_SET
MODE/PLLIN
EXTERNAL
OSCILLATOR
DIGITAL _SYNC
PHASE/
FREQUENCY
DETECTOR
FREQ
VCO
3867 F15
Figure 15. Phase-Locked Loop Block Diagram
Typically, the external clock (on the MODE/PLLIN pin) input
high threshold is 1.6V, while the input low threshold is 1V.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time duration
that the LTC3867 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
( ) ^tON(MIN)
<
V_OUT
V_IN f
3867f
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