LTC3867_15 Datasheet, PDF (10/36 Pages) Linear Technology – Low IQ, Dual 2-Phase Synchronous Step-Down Controller

LTC3867
BLOCK DIAGRAM
MODE/PLLIN
ITEMP
FREQ
MODE/SYNC
DETECT
TEMPSNS
EXTV_CC
4.7V
F
0.6V
F
PLL-SYNC
ITSD
5.3V
REG
IFAST
I_LIM
OSC
3k
I_COMP
S
RQ
–
+ ^IREV
IFAST
SLOPE
COMPENSATION
INTV_CC
UVLO
1
51k
SLOPE RECOVERY
I_THB
ACTIVE CLAMP
FCNT
ON
BURSTEN
SWITCH
LOGIC
AND
ANTISHOOT-
THROUGH
RUN
OV
UV
SLEEP
V_IN
0.6V
REF
0.55V
SS
RUN
EA
0.5V
1.22V
OV
1.25µA
I_{TH RC} ^CC1
RUN TK/SS CSS
V_IN
INTV_CC
BOOST
+
C_IN
V_IN
INTV_CC
TG
C_B
SW
SENSE⁺ D_B
SENSE^–
BG
PGND
C_VCC
M1
L1
M2
V_OUT
+
C_OUT
PGOOD
DIFFOUT
0.555V
V_FB
DIFFAMP
DIFF⁺
1/2
0.645V
SGND
20k
20k
DIFF^–
3867 BD
1.0µA/5.0µA
OPERATION
Main Control Loop
The LTC3867 uses a constant frequency, current mode
step-down architecture. During normal operation, the
top MOSFET is turned on every cycle when the oscillator
sets the RS latch, and turned off when the main current
comparator, I_CMP , resets the RS latch. The peak inductor
10
current at which I_CMP resets the RS latch is controlled by
the voltage on the I_TH pin, which is the output of the er-
ror amplifier, EA. The remote sense amplifier (DIFFAMP)
produces a signal equal to the differential voltage sensed
across the output capacitor divided down by the feedback
divider and re-references it to the local IC ground reference.
3867f