LTC3853 Datasheet, PDF (28/36 Pages) Linear Technology – Triple Output, Multiphase Synchronous Step-Down Controller

LTC3853
APPLICATIONS INFORMATION
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope to
the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
output load drops below the low current operation
threshold—typically 10% of the maximum designed cur-
rent level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB implemen-
tation. Variation in the duty cycle at a subharmonic rate
can suggest noise pickup at the current or voltage sensing
inputs or inadequate loop compensation. Overcompensa-
tion of the loop can be used to tame a poor PC layout if
regulator bandwidth optimization is not required. Only after
each controller is checked for its individual performance
should all controllers be turned on at the same time. A
particularly difficult region of operation is when one con-
troller channel is nearing its current comparator trip point
when another channel is turning on its top MOSFET. This
occurs around 33% and 66% duty cycle on a channel in
triple mode, due to the phasing of the internal clocks and
may cause minor duty cycle jitter.
Reduce V_IN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V_IN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between C_IN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
Design Example
As a design example for a three channel medium cur-
rent regulator, assume V_IN = 12V(nominal), V_IN =
20V(maximum), V_OUT1 = 5V, V_OUT2 = 3.3V, V_OUT3 = 1.2V,
I_MAX1,2,3 = 5A, and f = 500kHz (see Figure 13).
The regulated output voltages are determined by:
V_OUT
=
0.8V
•
⎛
⎝⎜
1+
R_B
R_A
⎞
⎠⎟
Using 20k 1% resistors from both V_FB nodes to ground,
the top feedback resistors are (to the nearest 1% standard
value) 105k, 63.4k and 10k.
The minimum on-time occurs on channel 3 at the maximum
V_IN, and should not be less than 90ns:
t_ON(MIN) =
V_OUT
V_IN(MAX) f
= ^1.2V = 120ns
20V(500kHz)
The frequency is set by biasing the FREQ/PLLFLTR pin to
1.2V (see Figure 10), using a divider from INTV_CC. This
voltage will decrease as V_IN approaches 5V, lowering the
switching frequency. If a separate 5V supply is connected to
EXTV_CC, INTV_CC will remain at 5V even if V_IN decreases.
The inductance values are based on a 35% ripple current
assumption (1.75A for each channel) at nominal input
voltage:
L=
f
V_OUT
• ΔI_L(NOM)
⎛
⎜^1−
⎝
V_OUT
V_IN(NOM)
⎞
⎟
⎠
Channel 1 will require 3.3μH, channel 2 will require 2.8μH
and channel 3 will require 1.25μH. The next highest
3853f
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