LTC3853 Datasheet, PDF (22/36 Pages) Linear Technology – Triple Output, Multiphase Synchronous Step-Down Controller

LTC3853
APPLICATIONS INFORMATION
time. The total RMS power lost is lower when more than
one controller is operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual or triple controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 3-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The sources of the top MOSFETs
should be placed within 1cm of each other and share a
common C_IN(s). Separating the sources and C_IN may pro-
duce undesirable voltage and current resonances at V_IN.
A small (0.1μF to 1μF) bypass capacitor between the chip
V_IN pin and ground, placed close to the LTC3853, is also
suggested. A 2.2Ω to 10Ω resistor placed between C_IN
(C1) and the V_IN pin provides further isolation between
the channels.
The selection of C_OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔV_OUT) is approximated by:
⎛
1⎞
ΔV_OUT ≈ I_{RIPPLE ⎝⎜}ESR + _{8fCOUT ⎠⎟}
where f is the operating frequency, C_OUT is the output
capacitance and I_RIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I_RIPPLE increases with input voltage.
Setting Output Voltage
The LTC3853 output voltages are each set by an external
feedback resistive divider carefully placed across the
output, as shown in Figure 9. The regulated output volt-
age is determined by:
V_OUT
=
0.8V
•
⎛
⎝⎜
1+
R_B
R_A
⎞
⎠⎟
V_OUT
1/3 LTC3853
V_FB
R_B
C_FF
R_A
3853 F09
Figure 9. Setting Output Voltage
To improve the frequency response, a feed-forward ca-
pacitor, C_FF, may be used. Great care should be taken to
route the V_FB line away from noise sources, such as the
inductor or the SW line.
Fault Conditions: Current Limit and Current Foldback
The LTC3853 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximum programmed value to one-third of the maximum
value. Foldback current limiting is disabled during the
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3853 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short-
circuit ripple current is determined by the minimum on-
time t_ON(MIN) of the LTC3853 (≈ 90ns), the input voltage
and inductor value:
ΔI_L(SC)
=
t_ON(MIN)
•
V_IN
L
The resulting short-circuit current is:
I_SC
=
1/3
V_SENSE(MAX)
R_SENSE
–
1
2 ^ΔIL(SC)
Phase-Locked Loop and Frequency Synchronization
The LTC3853 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET of
3853f
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