LTC3703-5_15 Datasheet, PDF (28/32 Pages) Linear Technology – 60V Synchronous Switching Regulator Controller

LTC3703-5
APPLICATIO S I FOR ATIO
estimated at maximum input voltage, assuming a junction
temperature of 100°C (30°C above an ambient of 70°C):
P_MAIN
=
12
60
(10)²_[1+
0.007(100
–
25)_](0.022)
+
(60)^{2 ⎛⎝⎜}
120⎞⎠⎟_(2)(200pF)
•
⎛⎝⎜
10
1
– 3.8
+
1
3.8
⎞⎠⎟_(250k)
= 0.67W + 0.76W = 1.43W
And double check the assumed T_J in the MOSFET:
T_J = 70°C + (1.43W)(20°C/W) = 99°C
Since the synchronous MOSFET will be conducting over
twice as long each period (almost 100% of the period in
short circuit) as the top MOSFET, use two Si7850DP
MOSFETs on the bottom:
P_SYNC = ^{⎛⎝⎜ 606−}₀₁₂^{⎞⎠⎟}(10)²_[1+ 0.007(100 – 25)_] •
⎛⎝⎜ 0.0222⎞⎠⎟ _{= 1.34W}
T_J = 70°C + (1.34W)(20°C/W) = 97°C
Next, set the current limit resistor. Since I_MAX = 10A, the
limit should be set such that the minimum current limit is
>10A. Minimum current limit occurs at maximum R_DS(ON).
Using the above calculation for bottom MOSFET T_J, the
max R_DS(ON) = (22mΩ/2) [1 + 0.007 (97-25)] = 16.5mΩ
Therefore, I_MAX pin voltage should be set to (10A)(0.0165)
= 0.165V. The R_SET resistor can now be chosen to be
0.165V/12µA = 14kΩ.
C_IN is chosen for an RMS current rating of about 5A
(I_MAX/2) at 85°C. For the output capacitor, two low ESR
OS-CON capacitors (18mΩ each) are used to minimize
output voltage changes due to inductor current ripple and
load steps. The ripple voltage will be:
∆V_OUT(RIPPLE) = ∆I_L(MAX) (ESR) = (4A)(0.018Ω/2)
= 36mV
However, a 0A to 10A load step will cause an output
voltage change of up to:
∆V_OUT(STEP) = ∆I_LOAD(ESR) = (10A)(0.009Ω)
= 90mV
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3703-5. These items are also illustrated graphically in
the layout diagram of Figure 20. For layout of a boost mode
converter, layout is similar with V_IN and V_OUT swapped.
Check the following in your layout:
1. Keep the signal and power grounds separate. The signal
ground consists of the LTC3703-5 GND pin, the ground
return of C_VCC, and the (–) terminal of V_OUT. The power
ground consists of the Schottky diode anode, the source
of the bottom side MOSFET, and the (–) terminal of the
input capacitor and DRV_CC capacitor. Connect the signal
and power grounds together at the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal of
the output capacitor as close as possible to the (–)
terminals of the input and DRV_CC capacitor and away from
the Schottky loop described in (2).
2. The high di/dt loop formed by the top N-channel
MOSFET, the bottom MOSFET and the C_IN capacitor
should have short leads and PC trace lengths to minimize
high frequency noise and voltage stress from inductive
ringing.
3. Connect the drain of the top side MOSFET directly to the
(+) plate of C_IN, and connect the source of the bottom side
MOSFET directly to the (–) terminal of C_IN. This capacitor
provides the AC current to the MOSFETs.
4. Place the ceramic C_DRVCC decoupling capacitor imme-
diately next to the IC, between DRV_CC and BGRTN. This
capacitor carries the MOSFET drivers’ current peaks.
Likewise the C_B capacitor should also be next to the IC
between BOOST and SW.
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