LTC3703-5_15 Datasheet, PDF (25/32 Pages) Linear Technology – 60V Synchronous Switching Regulator Controller

LTC3703-5
APPLICATIO S I FOR ATIO
MODE/SYNC Pin (External Synchronization)
The internal LTC3703-5 oscillator can be synchronized to
an external oscillator by applying and clocking the MODE/
SYNC pin with a signal above 2V_P-P. The internal oscillator
locks to the external clock after the second clock transi-
tion is received. When external synchronization is de-
tected, LTC3703-5 will operate in forced continuous
mode. If an external clock transition is not detected for
three successive periods, the internal oscillator will revert
to the frequency programmed by the R_SET resistor. The
internal oscillator can synchronize to frequencies be-
tween 100kHz and 600kHz, independent of the frequency
programmed by the R_SET resistor. However, it is recom-
mended that an R_SET resistor be chosen such that the
frequency programmed by the R_SET resistor is close to the
expected frequency of the external clock. In this way, the
best converter operation (ripple, component stress, etc)
is achieved if the external clock signal is lost.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time t_ON(MIN) is the smallest amount of time
that the LTC3703-5 is capable of turning the top MOSFET
on and off again. It is determined by internal timing delays
and the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimum on-time limit and care should be taken to ensure
that:
t_ON
=
V_OUT
V_IN • f
>
t_ON(MIN)
where t_ON(MIN) is typically 200ns.
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3703-5 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
t_ON(MIN) for the same step-down ratio.
Pin Clearance/Creepage Considerations
The LTC3703-5 is available in two packages (GN16 and
G28) both with identical functionality. The GN16 package
gives the smallest size solution, however the 0.013”
(minimum) space between pins may not provide sufficient
PC board trace clearance between high and low voltage
pins in higher voltage applications. Where clearance is an
issue, the G28 package should be used. The G28 package
has 4 unconnected pins between the all adjacent high
voltage and low voltage pins, providing 5(0.0106”) =
0.053” clearance which will be sufficient for most applica-
tions up to 60V. For more information, refer to the printed
circuit board design standards described in IPC-2221
(www.ipc.org).
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (x100%). Per-
cent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement. Al-
though all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3703-5 circuits: 1) LTC3703-5 V_CC current,
2) MOSFET gate current, 3) I²R losses and 4) Topside
MOSFET transition losses.
1. V_CC Supply current. The V_CC current is the DC supply
current given in the Electrical Characteristics table which
powers the internal control circuitry of the LTC3703-5.
Total supply current is typically about 2.5mA and usually
results in a small (<1%) loss which is proportional to V_CC.
2. DRV_CC current is MOSFET driver current. This current
results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched on and
then off, a packet of gate charge Q_G moves from DRV_CC to
ground. The resulting dQ/dt is a current out of the DRV_CC
supply. In continuous mode, I_DRVCC = f(Q_G(TOP) + Q_G(BOT)),
where Q_G(TOP) and Q_G(BOT) are the gate charges of the top
and bottom MOSFETs.
3. I²R losses are predicted from the DC resistances of
MOSFETs, the inductor and input and output capacitor
ESR. In continuous mode, the average output current
flows through L but is “chopped” between the topside
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