LTC3553_15 Datasheet, PDF (28/36 Pages) Linear Technology – Micropower USB Power Manager With Li-Ion Charger, LDO and Buck Regulator

LTC3553
OPERATION
Power-Down by De-Asserting Both BUCK_ON and
LDO_ON
Figure 11 shows the LTC3553 powering down by μC/μP
control. For this example the pushbutton circuitry starts in
the PON state with a battery connected and both regula-
tors enabled. The user presses the pushbutton (ON low)
for at least 50ms, which generates a debounced, low
impedance pulse on the PBSTAT output. After receiving
the PBSTAT signal, the μC/μP software decides to drive
both the BUCK_ON and LDO_ON inputs low in order to
power down. After the last input goes low, the pushbutton
circuitry will enter the PDN2 state. In the PDN2 state a one
second wait time is initiated after which the pushbutton
circuitry enters the POFF state. During this one second
time, the ON, BUCK_ON and LDO_ON inputs as well as
external power application are ignored to allow all LTC3553
generated supplies to go low. Though the above assumes
a battery present, the same operation would take place
1
BAT
0
1
V_BUS
0
1
ON (PB)
0
1
PBSTAT
0
1
BUCK_ON
0
1
LDO_ON
0
1
BUCK
0
1
LDO
0
STATE
PON
1s
50ms
µC/µP CONTROL
µC/µP CONTROL
PDN2
POFF
3553 TD04
Figure 11. Power-Down via De-Assertion of
BUCK_ON and LDO_ON
with a valid external supply (V_BUS) with or without a bat-
tery present.
Holding ON low through the one second power-down
period will not cause a power-up event at end of the one
second period. The ON pin must be brought high following
the power-down event and then go low again to establish
a valid power-up event.
UVLO Minimum Off-Time Timing (Low Battery)
Figure 12 assumes the battery is either missing or at a
voltage below the V_OUT UVLO threshold, and the appli-
cation is running via external power (V_BUS). A glitch on
the external supply causes V_OUT to drop below the V_OUT
UVLO threshold temporarily. This V_OUT UVLO condition
causes the pushbutton circuitry to transition from the PON
state to the PDN2 state. Upon entering the PDN2 state the
regulators power down together.
1
BAT
0
1
V_BUS
0
1
ON (PB)
0
1
PBSTAT
0
1
BUCK_ON
0
1
LDO_ON
0
1
BUCK
0
1
LDO
0
1
SEQ
0
STATE
PON
PDN2
5s
5s
1s, BUCK POWERS UP
LDO POWERS UP
PUP2
PON
3553 TD05
Figure 12. UVLO Minimum Off-Time Timing
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