LTC3553_15 Datasheet, PDF (24/36 Pages) Linear Technology – Micropower USB Power Manager With Li-Ion Charger, LDO and Buck Regulator

LTC3553
OPERATION
regulator, the LDO’s load capability remains unchanged.
However, the LDO’s transient response is slowed, as il-
lustrated in Figure 5 and Figure 6.
LDO OUTPUT
VOLTAGE
AC-COUPLED
0.1V/DIV
150mA
I_{LDO 5mA}
50µs/DIV
LDO REGULATING 3.3V
4.7µF OUTPUT CAPACITOR
STBY LOW
3553 F05
Figure 5. LDO Load Step Response in Normal Operation
measures should be taken to ensure that the buck is not
operated outside the specified BVIN input supply range,
as operation beyond this range is not guaranteed.
LDO Regulator UVLO Considerations
The LDO regulator’s bias current is supplied via an internal
connection to the USB PowerPath V_OUT pin. The V_OUT UVLO
shuts down the LDO when V_OUT drops below about 2.6V
in order to prevent the LDO from operating incorrectly
due to too low a bias supply voltage.
The LDO power input pin, V_INLDO, can be driven with as
little as 1.65V. There is, however, no UVLO to enforce
this requirement. It is thus recommended that V_INLDO be
tied to either the buck regulator output (programmed to
regulate at least 1.65V), or to the USB PowerPath V_OUT
pin, to ensure proper operation.
LDO OUTPUT
VOLTAGE
AC-COUPLED
0.1V/DIV
150mA
I_{LDO 5mA}
50µs/DIV
LDO REGULATING 3.3V
4.7µF OUTPUT CAPACITOR
STBY HIGH
3553 F06
Figure 6. LDO Load Step Response in Standby Mode
V_OUT UNDERVOLTAGE LOCKOUT (V_OUT UVLO)
An undervoltage lockout circuit on the USB PowerPath
V_OUT pin shuts down and prevents both the buck and
the LDO from enabling when the V_OUT pin voltage drops
below about 2.6V.
Buck Regulator UVLO Considerations
It is recommended that the buck regulator input supply
(BVIN pin) be connected directly to the USB PowerPath
output (V_OUT pin). With this connection, the V_OUT UVLO
prevents the buck regulator from operating at low input
supply voltages where loss of regulation or other unde-
sirable operation may occur. In applications where the
buck input is supplied from other than the V_OUT pin, other
24
PUSHBUTTON INTERFACE
State Diagram/Operation
Figure 7 shows the LTC3553 pushbutton state diagram.
The pushbutton state machine has a clock with a 1.82ms
period.
Upon first application of power, V_BUS or BAT, an inter-
nal power on reset (POR) signal places the pushbutton
circuitry into the power-down (PDN1) state. One second
PUP2
EXTPWR OR
PB400MS
HR
EXTPWR OR
PB400MS
5SEC
PUP1
5SEC
BUCK_ON 1SEC
OR LDO_ON
POFF
UVLO AND
EITHER BUCK_ON
OR LDO_ON
PON
HRST
1SEC
UVLO OR
BOTH BUCK_ON
AND LDO_ON
PDN2
HRST
HRST
PDN1
POR
3553 F07
Figure 7. Pushbutton State Diagram
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