LTC3553_15 Datasheet, PDF (23/36 Pages) Linear Technology – Micropower USB Power Manager With Li-Ion Charger, LDO and Buck Regulator

LTC3553
OPERATION
The switching regulator input supply should be bypassed
with a 2.2μF capacitor. Consult with capacitor manu-
facturers for detailed information on their selection and
specifications of ceramic capacitors. Many manufacturers
now offer very thin (<1mm tall) ceramic capacitors ideal
for use in height-restricted designs. Table 2 shows a list
of several ceramic capacitor manufacturers.
LOW DROPOUT LINEAR REGULATOR (LDO)
The LDO regulator supports a load of up to 150mA. The
LDO takes power from the V_INLDO pin and drives the LDO
output pin with the goal of bringing the LDO_FB feedback
pin voltage to 0.8V. Usually, a resistor divider is connected
between the LDO’s output pin, feedback pin and ground,
in order to close the control loop and program the output
voltage. For stability, the LDO output must be bypassed
to ground with at least a 1μF ceramic capacitor.
The LDO is enabled or disabled via the pushbutton interface.
In cases where the LDO is disabled and the PowerPath
is actively driving V_OUT, an internal pull-down resistor is
switched in to help bring the output to ground. When the
LDO is enabled, a soft-start circuit ramps its regulation
point from zero to final value over a period of roughly
0.2ms, reducing the required V_INLDO inrush current.
The LDO has two input voltage requirements. The LDO’s
quiescent bias current is supplied through an internal
connection to the USB PowerPath V_OUT pin. The LDO’s
power input is taken from the V_INLDO pin. For proper
LDO operation, the V_INLDO pin must be connected to a
voltage no greater than V_OUT. For example, V_INLDO can
be connected to V_OUT, or to the buck regulator output.
Connecting V_INLDO to a voltage exceeding V_OUT may result
in loss of regulation.
Output Voltage Programming
Figure 4 shows the LDO regulator application circuit.
Program the LDO output voltage, V_LDO, by choosing R1
and R2 such that:
V_LDO
=
0.8V
•


R1
R2
+
1^{}
LDO
ENABLE
0
1
V_INLDO
MP
LDO
R1
LDO_FB
0.8V
R2
GND
LDO
OUTPUT
C_OUT
3553 F04
Figure 4. LDO Application Circuit
Standby Mode LDO Operation (STBY Pin High)
To reduce battery drain current in applications with a
static memory keep-alive or other ultralow quiescent
current state, the LDO may be placed into standby mode
(together with the buck regulator). When the STBY pin is
brought high, LDO bias current is reduced. Unlike the buck
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