LTC3865-1_15 Datasheet, PDF (25/38 Pages) Linear Technology – Dual, 2-Phase Synchronous DC/DC Controller with Pin Selectable Outputs

LTC3865/LTC3865-1
APPLICATIONS INFORMATION
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f_OSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than f_OSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low thres-hold
is 1V. The external clock should not be applied when the
IC is in shutdown.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time duration
that the LTC3865/LTC3865-1 is capable of turning on the
top MOSFET. It is determined by internal timing delays
and the gate charge required to turn on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that
t_ON(MIN)
<
V_OUT
V_IN(f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3865/LTC3865-1 is
approximately 90ns, with reasonably good PCB layout,
minimum 30% inductor current ripple and at least 10mV
to 15mV ripple on the current sense signal. The mini-
mum on-time can be affected by PCB switching noise in
the voltage and current loop. As the peak sense voltage
decreases the minimum on-time gradually increases to
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3865/LTC3865-1 circuits: 1) IC V_IN current,
2) INTV_CC regulator current, 3) I²R losses, 4) Topside
MOSFET transition losses.
1. The V_IN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. V_IN current typi-
cally results in a small (<0.1%) loss.
2. INTV_CC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTV_CC to ground. The resulting dQ/dt is a cur-
rent out of INTV_CC that is typically much larger than the
control circuit current. In continuous mode, I_GATECHG
= f(Q_T + Q_B), where Q_T and Q_B are the gate charges of
the topside and bottom side MOSFETs.
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