LTC3828 Datasheet, PDF (25/32 Pages) Linear Technology – Dual 2-Phase Step-Down Controller with Tracking

LTC3828
APPLICATIO S I FOR ATIO
with a typical value of R_DS(ON) and δ= (0.005/°C)(20) = 0.1.
The resulting power dissipated in the bottom MOSFET is:
P_SYNC
=
22V – 1.8V
22V
(^2.1A)²
(^1.125)(^0.022Ω)
= 100mW
which is less than under full-load conditions.
C_IN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. C_OUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V_ORIPPLE = R_ESR (∆I_L) = 0.02Ω(1.67A) = 33mV_P–P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the
layout diagram of Figure 12. The Figure 13 illustrates the
current waveforms present in the various branches of the
2-phase synchronous regulators operating in the continu-
ous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at C_IN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C_INTVCC must return to the combined C_OUT (–) terminals.
The path formed by the top N-channel MOSFET, Schottky
diode and the C_IN capacitor should have short leads and
PC trace lengths. The output capacitor (–) terminals
should be connected as close as possible to the (–)
terminals of the input capacitor by placing the capacitors
next to each other and away from the Schottky loop
described above.
3. Do the LTC3828 V_OSENSE pins’ resistive dividers con-
nect to the (+) terminals of C_OUT? The resistive divider
must be connected between the (+) terminal of C_OUT and
signal ground. The R2 and R4 connections should not be
along the high current input feeds from the input
capacitor(s).
4. Are the SENSE ^– and SENSE ⁺ leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE ⁺ and SENSE ^– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.
5. Is the INTV_CC decoupling capacitor connected close to
the IC, between the INTV_CC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTV_CC and PGND pins can help improve noise
performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC3828 and occupy minimum PC trace area.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV_CC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
3828f
25