LTC3814-5_15 Datasheet, PDF (23/30 Pages) Linear Technology – 60V Current Mode Synchronous Step-Up Controller

LTC3814-5
APPLICATIONS INFORMATION
A reasonable assumption is that the minimum R_DS(ON)
lies the same percentage below the typical value as the
maximum lies above it. Consult the MOSFET manufacturer
for further guidelines.
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where V_OUT > V_IN.
For hard shorts, the inductor current is limited only by the
input supply capability.
Run/Soft-Start Function
The RUN/SS pin is a multipurpose pin that provides a soft-
start function and a means to shut down the LTC3814-5.
Soft-start reduces the input supply’s surge current by
controlling the ramp rate of the I_TH voltage, eliminates
output overshoot and can also be used for power supply
sequencing.
Pulling RUN/SS below 0.9V puts the LTC3814-5 into a low
quiescent current shutdown (I_Q = 224μA). This pin can be
driven directly from logic as shown in Figure 14. Releasing
the RUN/SS pin allows an internal 1.4μA current source to
charge up the soft-start capacitor, C_SS. When the voltage
on RUN/SS reaches 0.9V, the LTC3814-5 turns on and
begins ramping the I_TH voltage at V_ITH = V_SS – 0.9V. As the
RUN/SS voltage increases from 0.9V to 3.3V, the current
limit is increased from 0% to 100% of its maximum value.
The RUN/SS voltage continues to charge until it reaches
its internally clamped value of 4V.
If RUN/SS starts at 0V, the delay before starting is
approximately:
( ) ^t_DELAY,START
=
0.9V
1.4µA
C_SS
=
0.64s/µF
C_SS
plus an additional delay, before the current limit reaches
its maximum value of:
t_DELAY,REG
≥
2.4V
1.4µA
C_SS
The start delay can be reduced by using diode D1 in
Figure 13.
3.3V
OR 5V
RUN/SS
D1
C_SS
RUN/SS
C_SS
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Figure 13. RUN/SS Pin Interfacing
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3814-5 circuits:
1. DC I²R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause
the efficiency to drop at high input currents. The input
current is maximum at maximum output current and
minimum input voltage. The average input current flows
through L, but is chopped between the top and bottom
MOSFETs. If the two MOSFETs have approximately the
same R_DS(ON), then the resistance of one MOSFET can
simply be summed with the resistances of L and the
board traces to obtain the DC I²R loss. For example, if
R_DS(ON) = 0.01Ω and R_L = 0.005Ω, the loss will range
from 15mW to 1.5W as the input current varies from
1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the bottom MOSFET spends in the saturated
region during switch node transitions. It depends upon
the output voltage, load current, driver strength and
MOSFET capacitance, among other factors. The loss
is significant at output voltages above 20V and can be
estimated from the second term of the P_MAIN equa-
tion found in the Power MOSFET Selection section.
When transition losses are significant, efficiency can
be improved by lowering the frequency and/or using a
bottom MOSFET(s) with lower C_RSS at the expense of
higher R_DS(ON).
3. INTV_CC current. This is the sum of the MOSFET
driver and control currents. Control current is typically
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