LTC3708_15 Datasheet, PDF (23/32 Pages) Linear Technology – Fast 2-Phase, No RSENSE Buck Controller with Output Tracking

LTC3708
APPLICATIONS INFORMATION
Third, design the inductors for about 40% ripple current
at the maximum V_IN:
L1 =
2.5V
(^500kHz)(^0.4)(^10A)
⎛⎝⎜_1–
22.85VV ⎞⎠⎟
=
1.1μH
A standard 1μH inductor will result in 45% of ripple current
(4.5A) at worst case.
L2
=
1.8V
(^500kHz)(^0.4)(^10A)
⎛⎝⎜_1–
1.8V
28V
⎞⎠⎟
=
0.8μH
L2 can also use 1μH to save some BOM (Bill of Material)
cost; the resulting ripple current is 3.4A.
The selection of MOSFETs is simplified by the fact that both
channels have the same maximum output current. Select
the top and bottom MOSFETs for one channel and the
same MOSFETs can be used for the other. Take channel 1
for calculation and begin with the bottom synchronous
MOSFET. As stated previously in the Power MOSFET Se-
lection section, the major criterion in selecting the bottom
MOSFET is low R_DS(ON). Choose an Si4874 for example:
R_DS(ON) = 0.0083Ω (nom) 0.010Ω (max), θ_JA = 40°C/W.
The nominal sense voltage is:
V_SNS(NOM) = (10A)(1.3)(0.0083) = 108mV
Tying V_RNG1 to 1.1V will set the current sense voltage
range for a nominal value of 110mV with the current
limit occurring at 146mV. To check if the current limit is
acceptable, assume a junction temperature of about 80°C
above a 70°C ambient with ρ_150°C = 1.5:
I_LIMIT
≥
146mV
(^1.5)(^0.010Ω)
+
1
2
(^4.1A)
=
11.8A
and double check the assumed T_J in the MOSFET:
P_BOT
=
28V – 2.5V
28V
(^11.8A)²(^1.5)(^0.010Ω)
=
1.9W
T_J = 70°C + (1.90W)(40°C/W) = 146°
Because the top MOSFET is on for only a short time,
an Si4884 will be sufficient: R_DS(ON) = 0.0165Ω (max),
C_RSS = 190pF, V_GS(TH) = 1V, θ_JA = 42°C/W. Checking its
power dissipation at current limit with ρ_130°C = 1.6:
P_TOP
=
2.5V
28V
(^11.8A)²(^1.6)(^0.0165Ω)
+
(^0.5)(^28V)²
(^11.8A)(^190pF)(^500kHz)(^2Ω)^{⎛⎝⎜}
5V
1
–
1V
+
1
1V
⎞⎠⎟
= 0.33W + 1.10W = 1.43W
T_J = 70°C + (1.43W)(42°C/W) = 130°
The junction temperatures for both top and bottom
MOSFETs will be significantly less at nominal current, but
the above analysis shows that careful attention to PCB
layout and heat sinking will be necessary in this circuit.
The same MOSFETs (Si4874 and Si4884) can be used
for channel 2.
Finally, an input capacitor is chosen for an RMS current
rating of about 5A at 85°C and the output capacitors are
chosen for a low ESR of 0.013Ω to minimize output volt-
age changes due to inductor ripple current and load steps.
The ripple voltage will be only:
ΔV_OUT1(RIPPLE)
=
ΔI_L1
•
⎛⎝⎜_ESR
+
8
•
f
1
• C_OUT
⎞
⎠⎟
=
4.5A
•
⎛
⎝⎜
0.013Ω
+
8
•
1
500kHz
•
470μF
⎞
⎠⎟
= 60mV
ΔV_OUT2(RIPPLE)
=
ΔI_L2
•
⎛⎝⎜_ESR
+
8
•
f
1
• C_OUT
⎞
⎠⎟
=
3.4A
•
⎛
⎝⎜
0.013Ω
+
8
•
1
500kHz
•
470μF
⎞
⎠⎟
= 46mV
However, a 0A to 10A load step will cause an output
change of up to:
ΔV_OUT(STEP) = ΔI_LOAD(ESR) = (10A)(0.013Ω) = 130mV
An optional 22μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 13.
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