LTC4040_15 Datasheet, PDF (22/26 Pages) Linear Technology – 2.5A Battery Backup Power Manager

LTC4040
Applications Information
boost converter is V_BAT, the RHP zero frequency can be
expressed as follows:
( ) _fRHP
=
V_BAT ²
2 • π •L •P_OUT
•η
For the LTC4040’s backup boost to be able to supply
12.5W of output power (2.5A at 5V) from a 3.2V battery,
the maximum inductor size should not exceed 2.2µH be-
cause of the RHP zero consideration. Also, too much lead
resistance between the battery and the BAT pin can lower
the effective input voltage of the boost converter causing
the RHP zero to shift downward and cause instability.
This is why it is important to minimize the lead resistance
and place the battery as close to the BAT pin as possible.
Alternate NTC Thermistors and Biasing
The hot and cold trip points may be adjusted using a differ-
ent type of thermistor, or a different R_BIAS resistor, or by
adding a desensitizing resistor R_ADJ as shown in Figure 2,
or by a combination of these measures. For example, by
increasing R_BIAS to 12.4k from the default value of 10k,
with the same Vishay Curve 2 thermistor, the cold trip point
moves down to –5°C, and the hot trip point moves down to
34°C. If a Vishay Curve 1 thermistor with ß25/85 = 3950K
and resistor of 100k at 25°C is used, a 1% R_BIAS resistor
of 118k and a 1% R_ADJ resistor of 12.1k results in a cold
trip point of 0°C, and a hot trip point of 39°C.
LTC4040
TOO COLD
TOO HOT
BAT
V_IN
NTC
74% V_IN
29% V_IN
R_BIAS
R_ADJ
OPT
+
R_NTC
Li-Ion
IGNORE NTC
1.7% V_IN
4040 F01
Figure 2. NTC Connections
PCB Layout Considerations
Since the LTC4040 includes a high-current high-frequency
switching converter, the following guidelines should be used
during printed circuit board (PCB) layout in order to achieve
optimum performance and minimum electromagnetic
interference (EMI).
1. Even though the converter can operate in both step-
down (buck) and step-up (boost) mode, there is only
one hot-loop containing high-frequency switching
currents. The simplified diagram in Figure 3 can be
used to explain the hot-loop in the LTC4040 switching
converter. Current follows the blue loop when switch
S2 (NMOS) is closed and the red loop when switch
S1 (PMOS) is closed. So it is evident that the current
in the C_BAT capacitor is continuous whereas the C_SYS
current is discontinuous forming a hot loop with V_SYS
pins and GND as indicated by the green loop. Since the
amount of EMI is directly proportional to the area of
this loop, the V_SYS capacitor, prioritized over all else,
should be placed as close to the V_SYS pins as possible
and the ground side of the capacitor should return to
the ground plane through an array of vias.
V_BAT
+
C_BAT
S1
L1
S2
HOT LOOP
V_SYS
C_SYS
4040 F03
Figure 3. Hot-Loop Illustration for the LTC4040 Switching Converter
2. To minimize parasitic inductance, the ground plane
should be as close as possible to the top plane of the
PC board (Layer 2). High frequency currents in the hot
loop tend to flow along a mirror path on the ground
plane which is directly beneath the incident path on
the top plane of the board as illustrated in Figure 4. If
there are slits or cuts or drill-holes in this mirror path
on the ground plane due to other traces, the current will
be forced to go around the slits. When high frequency
currents are not allowed to flow back through their
4040fa
22
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