LTC4040_15 Datasheet, PDF (16/26 Pages) Linear Technology – 2.5A Battery Backup Power Manager

LTC4040
Operation
V_BAT > V_SYS Operation
The LTC4040 boost converter will maintain voltage regula-
tion even if its input voltage is above the output voltage.
This is achieved by terminating the switching of the syn-
chronous PMOS and applying V_BAT voltage statically on
its gate. This ensures that the slope of the inductor current
will reverse during the time current is flowing to the out-
put. Since the PMOS no longer acts as a low impedance
switch in this mode, there will be more power dissipation
within the IC. This will cause a sharp drop in the efficiency.
The maximum output current should be limited in order
to maintain an acceptable junction temperature.
INPUT CURRENT LIMIT AND CLPROG MONITOR
The LTC4040 contains an input current limit circuit which
monitors the total system current (the external load plus
the charger input current) via an external series resistor,
R_S, connected between the pins V_IN and CLN. The part
does not actually limit the external load but as the exter-
nal load demand increases, it reduces charge current, if
necessary, in an attempt to maintain a maximum of 25mV
across the V_IN and CLN pins. Please refer to Programming
the Input Current Limit and CLPROG Monitor section in
Applications Information. However, if the external load
demand exceeds the limit set by R_S, the part does not
reduce the load current but the charge current will drop
to zero. In all scenarios, the voltage on the CLPROG pin
will correctly represent the total system current. 800mV
on the CLPROG pin represents the full-scale current set
by the external series resistor, R_S.
Power-Fail COMPARATOR AND MODE SWITCHING
The LTC4040 contains a fast power-fail comparator which
switches the part from normal to backup mode in the
event the input supply voltage falls below an externally
programmed threshold voltage. This threshold voltage
is programmed by an external resistor divider via the PFI
pin. See the Applications Information section for details of
how to choose values for the resistor divider. The output
of the power-fail comparator also directly drives the gate
of an open-drain NMOS to report the status of the avail-
ability of input power via the PFO pin. If input power is
available, the PFO pin is high impedance; otherwise, the
pin is pulled down to ground.
At the onset of backup mode, the battery charger shuts
off, the external NMOS pass transistors (MN1 and MN2 in
Block Diagram) are quickly turned off by discharging IGATE
to ground thereby disconnecting the system output V_SYS
from the input and the backup boost converter activates
promptly to deliver load from the battery. Although the
power-fail comparator has a hysteresis of approximately
30mV, it may not be able to overcome the input voltage
spike resulting from the sudden collapse of the forward
current from the input to V_SYS. To prevent repeated un-
wanted mode switching, once activated, the backup boost
stays on for at least half a second. During this time, the
power-fail comparator output is ignored and an internal
switch of approximately 270Ω pulls down the OVSNS pin
to help discharge the input. After the half-second timer
expires, if the power-fail comparator output indicates that
power is still not available, the backup boost continues
to deliver the load but the pull-down on the OVSNS pin is
released. When the power-fail comparator detects that input
power is available, the OVP charge pump starts to charge
up the IGATE pin but the backup boost converter continues
to deliver system load until IGATE is approximately 8V.
This ensures that the forward conduction path through
the external NFET pass transistors has been established.
At this point, the backup boost gets deactivated and the
charger turns back on to charge the battery while the
system load gets delivered directly from the input to V_SYS
through the pass transistors.
Reset COMPARATOR
The LTC4040 contains a reset comparator which moni-
tors V_SYS under all operating modes via the RSTFB pin
and reports the status via an open-drain NMOS transistor
on the RST pin. At any time, if V_SYS falls 7.5% from its
programmed value, the RST pin pulls low almost instan-
taneously. However, the comparator waits approximately
232ms after V_SYS rises above the threshold before making
the RST pin high impedance. Please refer to Programming
the Reset Comparator Threshold section in Applications
Information.
4040fa
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