LTC3851-1_15 Datasheet, PDF (22/28 Pages) Linear Technology – Synchronous Step-Down Switching Regulator Controller

LTC3851-1
APPLICATIONS INFORMATION
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C_LOAD to C_OUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C_LOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3851-1. These items are also illustrated graphically
in the layout diagram of Figure 9. Check the following in
your layout:
1. Are the board signal and power grounds segregated?
The LTC3851-1 GND pin should tie to the ground plane
close to the input capacitor(s). The low current or signal
ground lines should make a single point tie directly to
the GND pin. The synchronous MOSFET source pins
should connect to the input capacitor(s) ground.
2. Does the V_FB pin connect directly to the feedback resis-
tors? The resistive divider R1, R2 must be connected
between the (+) plate of C_OUT and signal ground. The
47pF to 100pF capacitor should be as close as possible
to the LTC3851-1. Be careful locating the feedback
resistors too far away from the LTC3851-1. The V_FB
line should not be routed close to any other nodes with
high slew rates.
3. Are the SENSE^– and SENSE⁺ leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE⁺ and SENSE^– should be as close as
possible to the LTC3851-1. Ensure accurate current
sensing with Kelvin connections as shown in Figure 10.
Series resistance can be added to the SENSE lines to
increase noise rejection and to compensate for the ESL
of R_SENSE.
0.1mF
R_FREQ
1
16
MODE/PLLIN SW
2
15
FREQ/PLLFLTR TG
C_SS
R_C ^CC
47pF
3
RUN
14
BOOST
LTC3851-1
4
TK/SS
13
V_IN
C_C2
5
I_TH
12
INTV_CC
6
V_FB
11
BG
1000pF
7 _SENSE–
10
GND
8 _SENSE+
9
PGOOD
M1
D_B
C_B
+
4.7μF
R_PGOOD
V_PULL-UP
L1
C_IN
+
D1
M2
R1
C_OUT
R2
R_SENSE
+
V_IN
–
–
V_OUT
+
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Figure 9. LTC3851-1 Layout Diagram
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