LTC3851-1_15 Datasheet, PDF (17/28 Pages) Linear Technology – Synchronous Step-Down Switching Regulator Controller

LTC3851-1
APPLICATIONS INFORMATION
is low. When the topside MOSFET is to be turned on, the
driver places the C_B voltage across the gate source of the
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage, SW, rises to V_IN
and the BOOST pin follows. With the topside MOSFET on,
the boost voltage is above the input supply:
V_BOOST = V_IN + V_INTVCC
The value of the boost capacitor C_B needs to be 100 times
that of the total input capacitance of the topside MOSFET.
The reverse breakdown of the external Schottky diode
must be greater than V_IN(MAX).
Undervoltage Lockout
The LTC3851-1 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTV_CC voltage
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTV_CC is below
3.2V. To prevent oscillation when there is a disturbance
on the INTV_CC, the UVLO comparator has 400mV of preci-
sion hysteresis.
Another way to detect an undervoltage condition is to
monitor the V_IN supply. Because the RUN pin has a precision
turn-on reference of 1.25V, one can use a resistor divider
to V_IN to turn on the IC when V_IN is high enough.
C_IN Selection
In continuous mode, the source current of the top N-channel
MOSFET is a square wave of duty cycle V_OUT/V_IN. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
I_RMS
≅ I_O(MAX)
V_OUT
V_IN
⎛ _VIN
⎝⎜ ^V_OUT
– 1^{⎞⎠⎟ 1/2}
This formula has a maximum at V_IN = 2V_OUT, where I_RMS =
I_O(MAX)/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the manufacturer if there is any question.
C_OUT Selection
The selection of C_OUT is primarily determined by the
effective series resistance, ESR, to minimize voltage
ripple. The output ripple, ΔV_OUT, in continuous mode is
determined by:
ΔV_OUT
≈
ΔI_L
⎛
⎜ESR
⎝
+
1^⎞
8fC_OUT
⎟
⎠
where f = operating frequency, C_OUT = output capacitance
and ΔI_L = ripple current in the inductor. The output ripple is
highest at maximum input voltage since ΔI_L increases with
input voltage. Typically, once the ESR requirement for C_OUT
has been met, the RMS current rating generally far exceeds
the I_RIPPLE(P-P) requirement. With ΔI_L = 0.3I_OUT(MAX) and
allowing 2/3 of the ripple to be due to ESR, the output
ripple will be less than 50mV at maximum V_IN and:
C_OUT Required ESR < 2.2R_SENSE
C_OUT
>
1
8fR_SENSE
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guarantees
that the output capacitance does not significantly discharge
during the operating frequency period due to ripple current.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage at or below 50mV. The I_TH pin
OPTI-LOOP compensation components can be optimized
to provide stable, high performance transient response
regardless of the output capacitors selected.
The selection of output capacitors for applications with
large load current transients is primarily determined by the
voltage tolerance specifications of the load. The resistive
component of the capacitor, ESR, multiplied by the load
current change, plus any output voltage ripple must be
within the voltage tolerance of the load.
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