LTC3788-1 Datasheet, PDF (22/28 Pages) Linear Technology – 2-Phase, Dual Output Synchronous Boost Controller

LTC3788-1
APPLICATIONS INFORMATION
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is
in the feedback loop and is the filtered and compensated
control loop response.
The gain of the loop will be increased by increasing R_C
and the bandwidth of the loop will be increased by de-
creasing C_C. If R_C is increased by the same factor that C_C
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C_LOAD to C_OUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • C_LOAD. Thus, a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example for one channel, assume V_IN =
12V(nominal), V_IN = 22V (max), V_OUT = 24V, I_MAX = 4A,
V_SENSE(MAX) = 75mV, and f = 350kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
ΔI_L
=
V_IN
f •L
⎛
⎝⎜ ^1−
V_IN
V_OUT
⎞
⎠⎟
A 6.8μH inductor will produce a 30% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
The R_SENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
R_SENSE
≤
75mV
9.25A
=
0.008Ω
Choosing 1% resistors: R_A = 5k and R_B = 95.3k yields an
output voltage of 24.072V.
The power dissipation on the top side MOSFET can
be easily estimated. Choosing a Vishay Si7848BDP
MOSFET results in: R_DS(ON) = 0.012Ω, C_MILLER = 150pF.
At maximum input voltage with T(estimated) = 50°C:
P_MAIN
=
(24V − 12V)
(12V)²
24V
•
(4A)²
• ⎡⎣1+ (0.005)(50°C − 25°C)⎤⎦ • 0.008Ω
+ (1.7)(24V)^{3 4A} (150pF)(350kHz) = 0.7W
12V
C_OUT is chosen to filter the square current in the output.
The maximum output current peak is:
I_OUT(PEAK)
=
24
12
•
4
⎛
⎝⎜
1
+
31%⎞
2 ⎠⎟
=
9.3A
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 46.5mV (assuming ESR
dominate ripple).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 7. Figure 8 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Put the bottom N-channel MOSFETs MBOT1 and MBOT2
and the top N-channel MOSFETs MTOP1 and MTOP2
in one compact area with C_OUT.
37881f
22