LTC3788-1 Datasheet, PDF (12/28 Pages) Linear Technology – 2-Phase, Dual Output Synchronous Boost Controller

LTC3788-1
OPERATION
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3788-1 draws.
If one channel is shut down and the other channel is in
sleep mode, the LTC3788-1 draws only 125μA of quiescent
current. If both channels are in sleep mode, the LTC3788-1
draws only 200μA of quiescent current. In sleep mode,
the load current is supplied by the output capacitor. As
the output voltage decreases, the EA’s output begins to
rise. When the output voltage drops enough, the ITH pin
is reconnected to the output of the EA, the sleep signal
goes low, and the controller resumes normal operation
by turning on the bottom external MOSFET on the next
cycle of the internal oscillator.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the top external MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous current operation.
In forced continuous operation or when clocked by an
external clock source to use the phase-locked loop (see
the Frequency Selection and Phase-Locked Loop section),
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
rent is determined by the voltage on the ITH pin, just as
in normal operation. In this mode, the efficiency at light
loads is lower than in Burst Mode operation. However,
continuous operation has the advantages of lower output
voltage ripple and less interference to audio circuitry, as
it maintains constant-frequency operation independent
of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3788-1 operates in PWM pulse-skipping
mode at light loads. In this mode, constant-frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator I_CMP may remain tripped for several
cycles and force the external bottom MOSFET to stay off
for the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
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forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop (FREQ
and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3788-1’s controllers
can be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTV_CC, or programmed through an external resistor.
Tying FREQ to SGND selects 350kHz while tying FREQ to
INTV_CC selects 535kHz. Placing a resistor between FREQ
and SGND allows the frequency to be programmed between
50kHz and 900kHz, as shown in Figure 6.
A phase-locked loop (PLL) is available on the LTC3788-1
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3788-1’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of the first controller’s external bottom MOSFET
to the rising edge of the synchronizing signal. Thus, the
turn-on of the second controller’s external bottom MOS-
FET is 180 degrees out-of-phase to the rising edge of the
external clock source.
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of BG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3788-1’s PLL is from
approximately 55kHz to 1MHz, and is guaranteed to
lock to an external clock source whose frequency is be-
tween 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
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