LTC3788-1 Datasheet, PDF (20/28 Pages) Linear Technology – 2-Phase, Dual Output Synchronous Boost Controller

LTC3788-1
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3788-1 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a low pass filter
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked to
the rising edge of an external clock signal applied to the
PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET
is thus 180 degrees out-of-phase with the external clock.
The phase detector is an edge-sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC, then current is sourced continu-
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than f_OSC,
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
C_LP, holds the voltage at the VCO input.
Typically, the external clock (on PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is
1.2V.
Note that the LTC3788-1 can only be synchronized to an
external clock whose frequency is within range of the
LTC3788-1’s internal VCO, which is nominally 55kHz
to 1MHz. This is guaranteed to be between 75kHz and
850kHz.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
20
Table 1 summarizes the different states in which the FREQ
pin can be used.
Table 1.
FREQ PIN
0V
INTV_CC
Resistor
Any of the Above
PLLIN/MODE PIN
DC Voltage
DC Voltage
DC Voltage
External Clock
FREQUENCY
350kHz
535kHz
50kHz to 900kHz
Phase Locked to
External Clock
1000
900
800
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
37881 F06
Figure 6. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time duration
that the LTC3788-1 is capable of turning on the bottom
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on-
time limit.
In forced continuous mode, if the duty cycle falls below
what can be accommodated by the minimum on-time,
the controller will begin to skip cycles but the output will
continue to be regulated. More cycles will be skipped when
V_IN increases. Once V_IN rises above V_OUT, the loop works
to keep the top MOSFET on continuously. The minimum
on-time for the LTC3788-1 is approximately 110ns.
37881f