LTC3788-1 Datasheet, PDF (21/28 Pages) Linear Technology – 2-Phase, Dual Output Synchronous Boost Controller

LTC3788-1
APPLICATIONS INFORMATION
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the greatest improvement. Percent efficiency
can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3788-1 circuits: 1) IC V_IN current, 2) IN-
TV_CC regulator current, 3) I²R losses, 4) Bottom MOSFET
transition losses.
1. The V_IN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. V_IN current typically results
in a small (<0.1%) loss.
2. INTV_CC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOS-
FETs. Each time a MOSFET gate is switched from low to
high to low again, a packet of charge, dQ, moves from
INTV_CC to ground. The resulting dQ/dt is a current out
of INTV_CC that is typically much larger than the control
circuit current. In continuous mode, I_GATECHG = f(Q_T +
Q_B), where Q_T and Q_B are the gate charges of the topside
and bottom side MOSFETs.
3. DC I²R losses. These arise from the resistances of
the MOSFETs, sensing resistor, inductor and PC board
traces and cause the efficiency to drop at high output
currents.
4. Transition losses apply only to the bottom MOSFET(s),
and become significant only when operating at low input
voltages (typically 15V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7)
V_OUT ³
V_IN
I_O(MAX) • C_RSS f
Other hidden losses, such as copper trace and internal
battery resistances, can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system-level losses during the
design phase.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V_OUT shifts by an
amount equal to ΔI_LOAD (ESR), where ESR is the effective
series resistance of C_OUT. ΔI_LOAD also begins to charge
or discharge C_OUT generating the feedback error signal
that forces the regulator to adapt to the current change and
return V_OUT to its steady-state value. During this recovery
time V_OUT can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior, but it also
provides a DC coupled and AC filtered closed loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I_TH
external components shown in Figure 9 circuit will provide
an adequate starting point for most applications.
The I_TH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is complete
and the particular output capacitor type and value have
been determined. The output capacitors must be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Placing a power MOSFET and load resistor directly across
the output capacitor and driving the gate with an ap-
propriate signal generator is a practical way to produce
37881f
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