LTC3112_15 Datasheet, PDF (22/32 Pages) Linear Technology – 15V, 2.5A Synchronous Buck-Boost DC/DC Converter

LTC3112
Applications Information
then verify that sufficient phase margin exists across all
other operating conditions. In this example application, at
V_IN = 3.5V and the full 1A load current, the right half plane
zero will be located at 60kHz and this will be a dominant
factor in determining the bandwidth of the control loop.
The first step in designing the compensation network is
to determine the target crossover frequency for the com-
pensated loop. A reasonable starting point is to assume
that the compensation network will generate a peak phase
boost of approximately 60°. Therefore, in order to obtain
a phase margin of 60°, the loop crossover frequency, f_C,
should be selected as the frequency at which the phase
of the buck-boost converter reaches −180°. As a result,
at the loop crossover frequency the total phase will be
simply the 60° of phase provided by the error amplifier
as shown below.
Phase Margin = f_BUCK-BOOST + f_{ERRORAMPLIFIER} + 180°
= –180° + 60° + 180° = 60°
Similarly, if a phase margin of 45° is required, the target
crossover frequency should be picked as the frequency
at which the buck-boost converter phase reaches −195°
so that the combined phase at the crossover frequency
yields the desired 45° of phase margin.
This example will be designed for a 60° phase margin to
ensure adequate performance over parametric variations
and varying operating conditions. As a result, the target
crossover frequency, f_C, will be the point at which the phase
of the buck-boost converter reaches −180°. It is generally
difficult to determine this frequency analytically given that
it is significantly impacted by the Q factor of the resonance
in the power stage. As a result, it is best determined from a
Bode plot of the buck-boost converter as shown in Figure 9.
This Bode plot is for the LTC3112 buck-boost converter
using the previously specified power stage parameters
and was generated from the small signal model equations
using LTSpice^®. In this case, the phase reaches −180° at
35kHz making f_C = 35kHz the target crossover frequency
for the compensated loop.
50
0
PHASE
–50
50
GAIN
0
–50
–100
–100
–150
–150
–200
–250
10
–200
f_C
100
1k
10k 100k
FREQUENCY (Hz)
–250
1M
3112 F09
Figure 9. Converter Bode Plot, V_IN = 3.5V, I_LOAD = 1A
From the Bode plot of Figure 9 the gain of the power stage
at the target crossover frequency is 7dB. Therefore, in
order to make this frequency the crossover frequency
in the compensated loop, the total loop gain at f_C must
be adjusted to 0dB. To achieve this, the gain of the com-
pensation network must be designed to be –7dB at the
crossover frequency.
At this point in the design process, there are three con­
straints that have been established for the compensation
network. It must have −7dB gain at f_C = 35kHz, a peak phase
boost of 60° and the phase boost must be centered at
f_C = 35kHz. One way to design a compensation network to
meet these targets is to simulate the compensated error
amplifier Bode plot in LTSpice for the typical compensation
network shown on the front page of this data sheet. Then,
the gain, pole frequencies and zero frequencies can be
iteratively adjusted until the required constraints are met.
Alternatively, an analytical approach can be used to design
a compensation network with the desired phase boost,
center frequency and gain. In general, this procedure can
be cumbersome due to the large number of degrees of
freedom in a Type III compensation network. However the
design process can be simplified by assuming that both
compensation zeros occur at the same frequency, f_Z, and
3112fc
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