LTC3112_15 Datasheet, PDF (21/32 Pages) Linear Technology – 15V, 2.5A Synchronous Buck-Boost DC/DC Converter

LTC3112
Applications Information
f_ZERO1
=
1
2πR_FB
C_FB
f_ZERO2
=
1
2π₍R_TOP +R_FF
)^C_FF
≅
1
2πR_TOP C_FF
f_POLE2
=
C_FB + C_POLE
2πC_FBC_POLE R_FB
≅
1
2π C_POLE R_FB
f_POLE3
=
1
2πC_FF R_FF
the phase contributed by this additional pole is negligible.
However, for loops with higher crossover frequencies this
additional phase loss should be taken into account when
designing the compensation network.
0.8V +
FB
–
V_COMP
LTC3112
R_FILT
INTERNAL
C_FILT^VCOMP
3112 F08
Figure 8. Internal Loop Filter.
In most applications the compensation network is de-
signed so that the loop crossover frequency is above the
resonant frequency of the power stage, but sufficiently
below the boost mode right half plane zero to minimize
the additional phase loss. Once the crossover frequency
is decided upon, the phase boost provided by the com-
pensation network is centered at that point in order
to maximize the phase margin. A larger separation in
frequency between the zeros and higher order poles will
provide a higher peak phase boost but may also increase
the gain of the error amplifier which can push out the loop
crossover to a higher frequency.
The Q of the power stage can have a significant influence
on the design of the compensation network because it
determines how rapidly the 180° of phase loss in the power
stage occurs. For very low values of series resistance, R_S,
the Q will be higher and the phase loss will occur sharply.
In such cases, the phase of the power stage will fall rapidly
to –180° above the resonant frequency and the total phase
margin must be provided by the compensation network.
However, with higher losses in the power stage (larger
R_S) the Q factor will be lower and the phase loss will occur
more gradually. As a result, the power stage phase will
not be as close to –180° at the crossover frequency and
less phase boost is required of the compensation network.
The LTC3112 error amplifier is designed to have a fixed
maximum bandwidth in order to provide rejection of
switching noise to prevent it from interfering with the
control loop. From a frequency domain perspective, this
can be viewed as an additional single pole as illustrated
in Figure 8. The nominal frequency of this pole is 400kHz.
For typical loop crossover frequencies below about 60kHz
Loop Compensation Example
This section provides an example illustrating the design
of a compensation network for a typical LTC3112 applica-
tion circuit. In this example a 5V regulated output voltage
is generated with the ability to supply a 1A load from an
input power source ranging from 3.5V to 15V. The nominal
750kHz switching frequency has been chosen. In this ap-
plication the maximum inductor current ripple will occur
at the highest input voltage. An inductor value of 4.7µH
has been chosen to limit the worst case inductor current
ripple to approximately 1A. A low ESR output capacitor
with a value of 47µF is specified to yield a worst case
output voltage ripple (occurring at the worst case step-up
ratio and maximum load current) of approximately 10mV.
In summary, the key power stage specifications for this
LTC3112 example application are given below.
f = 0.75MHz, t_LOW = 0.2µs
V_IN = 3.5V to 15V
V_OUT = 5V at 1A
C_OUT = 47µF, R_C = 5mΩ
L = 4.7µH, R_L = 50mΩ
With the power stage parameters specified, the compen­
sation network can be designed. In most applications,
the most challenging compensation corner is boost
mode operation at the greatest step-up ratio and highest
load current since this generates the lowest frequency
right half plane zero and results in the greatest phase
loss. Therefore, a reasonable approach is to design the
compensation network at this worst case corner and
3112fc
For more information www.linear.com/LTC3112
21