LTC3112_15 Datasheet, PDF (16/32 Pages) Linear Technology – 15V, 2.5A Synchronous Buck-Boost DC/DC Converter

LTC3112
Applications Information
CAPACITOR VENDOR INFORMATION
Both the input bypass capacitors and output capacitors
used with the LTC3112 must be low ESR and designed
to handle the large AC currents generated by switching
converters. This is important to maintain proper functioning
of the IC and to reduce ripple on both the input and output.
Many modern low voltage ceramic capacitors experience
significant loss in capacitance from their rated value with
increased DC bias voltages. For example, it is not uncom-
mon for a small surface mount ceramic capacitor to lose
50% or more of its rated capacitance when operated near
its rated voltage. As a result, it is sometimes necessary to
use a larger value capacitance or a capacitor with a higher
voltage rating then required in order to actually realize
the intended capacitance at the full operating voltage. For
details, consult the capacitor vendor’s curve of capacitance
versus DC bias voltage.
The capacitors listed in Table 2 provide a sampling of small
surface mount ceramic capacitors that are well suited to
LTC3112 application circuits. All listed capacitors are either
X5R or X7R dielectric in order to ensure that capacitance
loss overtemperature is minimized.
Table 2. Representative Bypass and Output Capacitors
PART NUMBER
VALUE VOLTAGE SIZE (mm)
(µF) (V)
L×W×H
AVX LD103D226MAB2A
22
25 3.2 × 2.5 × 2.79
Kemet C1210C476M4PAC7025
47
16 3.2 × 2.5 × 2.5
Murata GRM32ER61E226KE15L
22
25 3.6 × 2.5 × 2.5
Taiyo Yuden EMK325BJ476MM-T 47
16 3.2 × 2.5 × 2.5
TDK C5750X5RIC476M
47
16
5.7 × 5 × 2.3
PCB LAYOUT CONSIDERATIONS
The LTC3112 switches large currents at high frequencies.
Special attention should be paid to the PCB layout to ensure
a stable, noise-free and efficient application circuit. Figure 3
presents a representative 4-layer PCB layout to outline
some of the primary considerations. A few key guidelines
are outlined below:
1. A 4-layer board is highly recommended for the LTC3112
to ensure stable performance over the full operating
voltage and current range. A dedicated/solid ground
plane should be placed directly under the V_IN, V_OUT,
SW1 and SW2 traces to provide a mirror plane to
minimize noise loops from high dI/dt and dV/dt edges
(see Figure 3, 2nd layer).
2. All circulating high current paths should be kept as
short as possible. Capacitor ground connections
should via down to the ground plane in the shortest
route possible. The bypass capacitors on V_IN should be
placed as close to the IC as possible and should have
the shortest possible paths to ground (see Figure 3,
top layer).
3. The exposed pad is the power ground connection for
the LTC3112. Multiple vias should connect the back
pad directly to the ground plane. In addition maximi-
zation of the metallization connected to the back pad
will improve the thermal environment and improve
the power handling capabilities of the IC.
4. The high current components and their connections
should all be placed over a complete ground plane to
minimize loop cross-sectional areas. This minimizes
EMI and reduces inductive drops.
5. Connections to all of the high current components
should be made as wide as possible to reduce the
series resistance. This will improve efficiency and
maximize the output current capability of the buck-
boost converter.
6. To prevent large circulating currents from disrupting
the output voltage sensing, the ground for each resistor
divider should be returned to the ground plane using
a via placed close to the IC and away from the power
connections.
7. Keep the connection from the resistor dividers to the
feedback pins FB as short as possible and away from
the switch pin connections.
8. Crossover connections should be made on inner cop-
per layers if available. If it is necessary to place these
on the ground plane, make the trace on the ground
plane as short as possible to minimize the disruption
to the ground plane (see Figure 3, 3rd layer).
3112fc
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For more information www.linear.com/LTC3112