LTC3734_15 Datasheet, PDF (21/28 Pages) Linear Technology – Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3734
APPLICATIONS INFORMATION
output. Efficiency varies as the inverse square of V_OUT for
the same external components and output power level.
The combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input volt-
ages (typically 12V or greater). Transition losses can be
estimated from:
Transition Loss =
V_IN2
• ^IOUT
2
• f • C_RSS
• R_DR
•

1
1^


V_DR
–
V_TH(MIN)
+
V_TH(MIN)


3) PV_CC drives both top and bottom MOSFETs. The MOSFET
driver current results from switching the gate capacitance
of the power MOSFETs. Each time a MOSFET gate is
switched from low to high to low again, a packet of charge
dQ moves from PV_CC to ground. The resulting dQ/dt is a
current out of PV_CC that is typically much larger than the
control circuit current. In continuous mode, I_GATECHG =
(Q_T + Q_B)f, where Q_T and Q_B are the gate charges of the
topside and bottom side MOSFETs and f is the switching
frequency.
4) The input capacitor has the difficult job of filtering the
large RMS input current to the regulator. It must have a
very low ESR to minimize the AC I²R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
Other losses, including C_OUT ESR loss, Schottky diode
conduction loss during dead time, inductor core loss and
internal control circuitry supply current generally account
for less than 2% additional loss.
Checking Transient Response
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V_OUT shifts by an
amount equal to ∆I_LOAD(ESR), where ESR is the effective
series resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return V_OUT to its steady-state value. During this recovery
time V_OUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the I_TH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The I_TH external components shown
in the Figure 1 circuit will provide an adequate starting
point for most applications.
The I_TH series R_C-C_C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon first because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of <1µs will
produce output voltage and I_TH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step result-
ing from the step change in output current may not be
within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why
it is better to look at the I_TH pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased
by increasing R_C and the bandwidth of the loop will be
increased by decreasing C_C. If R_C is increased by the
same factor that C_C is decreased, the zero frequency will
be kept the same, thereby keeping the phase the same in
the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
3734fa
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