LTC3734_15 Datasheet, PDF (10/28 Pages) Linear Technology – Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3734
OPERATION (Refer to Functional Diagram)
Main Control Loop
The LTC3734 uses a constant frequency, current mode
step-down architecture. During normal operation, the top
MOSFET is turned on when the clock sets the RS latch,
and turned off when the main current comparator, I₁,
resets the RS latch. The peak inductor current at which I₁
resets the RS latch is controlled by the voltage on the I_TH
pin, which is the output of error amplifier EA. The V_FB pin
receives the voltage feedback signal, which is compared
to the internal reference voltage by the EA. When the
load current increases, it causes a slight decrease in EA
inverting input node relative to the 0.6V reference, which
in turn causes the I_TH voltage to increase until the average
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by current comparator I₂, or the beginning of
the next cycle.
The top MOSFET driver is biased from a floating bootstrap
capacitor C_B, which normally is recharged during each off
cycle through an external diode when the top MOSFET
turns off. As V_IN decreases to a voltage close to V_OUT,
the loop may enter dropout and attempt to turn on the
top MOSFET continuously. The dropout detector detects
this and forces the top MOSFET off for about 500ns every
sixth cycle to allow C_B to recharge.
The main control loop is shut down by pulling the RUN/
SS pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge soft-start capacitor C_SS. When
C_SS reaches 1.5V, the main control loop is enabled with
the internal I_TH voltage clamped at approximately 30%
of its maximum value. As C_SS continues to charge, the
internal I_TH voltage is gradually released allowing normal,
full-current operation.
Frequency Programming
The switching frequency of the LTC3734 is determined by
the DC voltage at the FREQSET pin. A DC voltage ranging
from 0V to 2.4V moves the internal oscillator frequency
from 210kHz to 550kHz.
Low Current Operation (PSIB)
The PSIB pin selects between two modes of operation.
When PSIB is above 0.6V, the controller operates in full
synchronous switching mode. Bottom driver (BG) is kept
on once it is turned on until the oscillator sets the RS latch.
The inductor current can therefore go from output back to
input power supply and could potentially boost the input
supply to dangerous voltage levels—BEWARE! This mode
of operation is also of lower efficiency and much current
can circulate between input and output. However, this
mode provides constant switching frequency.
When PSIB is below 0.6V, the bottom driver (BG) is turned
off if the inductor current starts to reverse. This mode
of operation prevents current going from output back to
input and eliminates the conduction power loss related to
circulating current. The circuit may skip switching cycles
at very light load conditions.
Output Voltage at Start-Up and at Deeper Sleep State
Under normal conditions, the output voltage of the regula-
tor is commanded by six VID bits, except at start-up and
at deeper sleep state. At start-up, the RUN/SS capacitor
starts to charge up and its voltage limits the inrush current
from the input power source. This linearly rising current
limit provides a controlled output voltage rise. During
start-up, the VID command is ignored and the output set
point is determined by the value of the resistor connected
to the RBOOT pin. The VID bits continue to be ignored for
15 switching cycles after the completion of the following
two conditions: 1) output voltage has risen up and has
regulated 2) MCH_PG signal has asserted. After 15 switch-
ing cycles, output voltage is fully commanded by VID bits.
In deeper sleep state, the VID command is also ignored
and the output set point is determined by the parallel value
of the resistors at the RDPRSLP pin and RDPSLP pin.
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