LTC3734_15 Datasheet, PDF (15/28 Pages) Linear Technology – Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs

LTC3734
APPLICATIONS INFORMATION
This simple worst-case condition is commonly used for
design, considering input/output variations and long term
reliability. Note that capacitor manufacturer’s ripple cur-
rent ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor,
or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paral-
leled to meet size or height requirements in the design.
Always consult the capacitor manufacturer if there is any
question.
The selection of C_OUT is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment has been met, the RMS current rating generally far
exceeds the I_RIPPLE(P-P) requirements. The steady state
output ripple (∆V_OUT) is determined by:
∆V_OUT
≈

∆I_{L } ESR
+
1
8fC_OUT


Where f = operating frequency of each stage, C_OUT = output
capacitance and ∆I_L is inductor peak-to-peak ripple current.
The LTC3734 employs OPTI-LOOP technique to compen-
sate the switching regulator loop with external components
(through I_TH pin). OPTI-LOOP compensation speeds
up regulator’s transient response, minimizes output
capacitance and effectively removes constraints on output
capacitor ESR. It opens a much wider selection of output
capacitor types and a variety of capacitor manufactures are
available for high current, low voltage switching regulators.
Manufacturers such as Nichicon, United Chemicon
and Sanyo should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
dielectric capacitor available from Sanyo has the lowest
(ESR)(size) product of any aluminum electrolytic at a
somewhat higher price. An additional ceramic capacitor
in parallel with OS-CON type capacitors is recommended
to reduce the inductance effects.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current han-
dling requirements of the application. Aluminum electrolytic
and dry tantalum capacitors are both available in surface
mount configurations. New special polymer (SP) surface
mount capacitors from Panasonic offer very low ESR also
but have much lower capacitive density per unit volume.
In the case of tantalum, it is critical that the capacitors are
surge tested for use in switching power supplies. Several
excellent choices are the AVX TPS, AVX TPSV or the KE-
MET T510 series of surface mount tantalums, available in
case heights ranging from 2mm to 4mm. Other capacitor
types include Sanyo OS-CON, POSCAPs, Kemet AO-CAPs,
Nichicon PL series and Sprague 595D series. Consult
the manufacturer for other specific recommendations. A
combination of capacitors will often result in maximizing
performance and minimizing overall cost and size.
PV_CC and SV_CC Decoupling
The PV_CC pin supplies power to the bottom gate driver
and therefore must be bypassed to power ground with a
minimum of 4.7µF ceramic or tantalum capacitor. Since
the gate driving currents are of high amplitude and high
slew rate, this bypassing capacitor should be placed very
close to the PV_CC and PGND pins to minimize the parasitic
inductance. Do NOT apply greater than 7V to the PV_CC pin.
The SV_CC pin supplies current to the internal control
circuitry of the LTC3734. This supply current is much
lower than that of the current for the external MOSFET
gate drive. Ceramic capacitors are very good for high
frequency filtering and a 0.1µF ~ 1µF ceramic capacitor
should be placed adjacent to the SV_CC and SGND pins.
Topside MOSFET Driver Supply (C_B,D_B) (Refer to
Functional Diagram)
External bootstrap capacitor C_B connected to the BOOST pin
supplies the gate drive voltages for the topside MOSFETs.
Capacitor C_B in the Functional Diagram is charged though
diode D_B from PV_CC when the SW pin is low. When the
topside MOSFET turns on, the driver places the C_B volt-
age across the gate-source of the desired MOSFET. This
enhances the MOSFET and turns on the topside switch.
The switch node voltage, SW, rises to V_IN and the BOOST
pin rises to V_IN + PV_CC. The value of the boost capacitor C_B
needs to be 30 to 100 times that of the total input capaci-
tance of the topside MOSFET(s). The reverse breakdown
of D_B must be greater than PV_CC(MAX).
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