LTC3729_15 Datasheet, PDF (19/30 Pages) Linear Technology – 550kHz, PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulator

LTC3729
APPLICATIONS INFORMATION
400kHz. The nominal operating frequency range of the
LTC3729 is 250kHz to 550kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex‑
ternal and internal oscillators. This type of phase detector
will not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, ∆f_H,
is equal to the capture range, ∆f_C:
∆f_H = ∆f_C = ±0.5 f_O (250kHz-550kHz)
The output of the phase detector is a complementary pair of
current sources charging or discharging the external filter
network on the PLLFLTR pin. A simplified block diagram
is shown in Figure 7.
EXTERNAL
OSC
2.4V
PHASE
DETECTOR
PLLIN
DIGITAL
PHASE/
FREQUENCY
50k
DETECTOR
R_LP
10k
C_LP
PLLFLTR
OSC
3729 F07
Figure 7. Phase-Locked Loop Block Diagram
If the external frequency (f_PLLIN) is greater than the os‑
cillator frequency f_0SC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency is
less than f_0SC, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLLFLTR
pin is adjusted until the phase and frequency of the ex‑
ternal and internal oscillators are identical. At this stable
operating point the phase comparator output is open and
the filter capacitor C_LP holds the voltage. The LTC3729
PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin. When us‑
ing multiple LTC3729’s for a phase-locked system, the
PLLFLTR pin of the master oscillator should be biased at
a voltage that will guarantee the slave oscillator(s) ability
to lock onto the master’s frequency. A DC voltage of
0.7V to 1.7V applied to the master oscillator’s PLLFLTR
pin is recommended in order to meet this requirement.
The resultant operating frequency will be approximately
500kHz.
The loop filter components (C_LP, R_LP) smooth out the cur‑
rent pulses from the phase detector and provide a stable
input to the voltage controlled oscillator. The filter compo‑
nents C_LP and R_LP determine how fast the loop acquires
lock. Typically R_LP =10k and C_LP is 0.01µF to 0.1µF.
Minimum On-Time Considerations
Minimum on-time t_ON(MIN) is the smallest time duration
that the LTC3729 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
( ) ^tON(MIN)
<
V_OUT
V_IN f
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3729 will begin to skip
cycles resulting in nonconstant frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the LTC3729 is approximately
100ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases. This is of
particular concern in forced continuous applications with
low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with cor‑
respondingly larger current and voltage ripple.
If an application can operate close to the minimum on-time
limit, an inductor must be chosen that has a low enough
inductance to provide sufficient ripple amplitude to meet
the minimum on-time requirement. As a general rule,
keep the inductor ripple current of each phase equal to or
greater than 15% of I_OUT(MAX)/N at V_IN(MAX).
3729fb
19