LTC3729_15 Datasheet, PDF (14/30 Pages) Linear Technology – 550kHz, PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulator

LTC3729
APPLICATIONS INFORMATION
( ) P_MAIN
=
V_OUT
V_IN


I_MAX
N


2
1+ d
R_DS(ON) +
k
(
V_IN
)²


I_MAX
N


(^C_RSS
)
(
f)
( ) P_SYNC
=
V_IN
– V_OUT
V_IN


I_MAX
N
²

1+ d
R_DS(ON)
where d is the temperature dependency of R_DS(ON), k is a
constant inversely related to the gate drive current and N
is the number of stages.
Both MOSFETs have I²R losses but the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V_IN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for V_IN > 20V the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_RSS actual provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + d) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs. Temperature curve,
but d = 0.005/°C can be used as an approximation for
low voltage MOSFETs. C_RSS is usually specified in the
MOSFET characteristics. The constant k = 1.7 can be used
to estimate the contributions of the two terms in the main
switch dissipation equation.
The Schottky diodes, D1 and D2 shown in Figure 1 conduct
during the dead-time between the conduction of the two large
power MOSFETs. This helps prevent the body diode of the
bottom MOSFET from turning on, storing charge during the
dead-time, and requiring a reverse recovery period which
would reduce efficiency. A 1A to 3A (depending on output
current) Schottky diode is generally a good compromise for
both regions of operation due to the relatively small average
current. Larger diodes result in additional transition losses
due to their larger junction capacitance.
14
C_IN and C_OUT Selection
In continuous mode, the source current of each top
N‑channel MOSFET is a square wave of duty cycle
V_OUT/V_IN. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a close form
equation can be found in Application Note 77. Figure 4
shows the input capacitor ripple current for different phase
configurations with the output voltage fixed and input volt‑
age varied. The input ripple current is normalized against
the DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(V_OUT), is approximately equal to the
input voltage V_IN or:
V_OUT
V_IN
=
k
N
where k = 1, 2, …, N – 1
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.
In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:
V_{OUT =} 2k − 1
V_IN 2N
where k = 1, 2, …, N
0.6
0.5
1-PHASE
0.4
2-PHASE
3-PHASE
0.3
4-PHASE
6-PHASE
0.2
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V_OUT/V_IN)
3729 F04
Figure 4. Normalized Input RMS Ripple Current vs
Duty Factor for 1 to 6 Output Stages
These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.
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