LTC3770_15 Datasheet, PDF (18/24 Pages) Linear Technology – Fast No RSENSE Step-Down Synchronous Controller with Margining, Tracking and PLL

LTC3770
APPLICATIONS INFORMATION
Margining
Margining is a way to program the reference voltage to
the error amplifier to a voltage different from the default
0.6V. Margining is useful for customers who want to
stress their systems by varying supply voltages during
testing. The reference voltage to the error amplifier is set
according to the following equation when the margining
function is enabled:
V_REFIN = 0.6V ±(1.18V/R4) • R3
Referring to the functional diagram, 0.6V is the buffered
system reference at the V_REFOUT pin. R3 and R4 are resistors
used for programming the amount of margining. V_REFIN
should be a voltage between 0.5V and 1V.
There are two logic control pins, MARGIN1 and MARGIN0,
to determine whether the margining function is enabled,
Margin up(+) or Margin down(–). Table 1 summarizes
the configurations:
Table 1. Margining Function
MARGIN1
MARGIN0
LOW
LOW
LOW
HIGH
HIGH
LOW
HIGH
HIGH
MODE
No Margining
Margin Up
Margin Down
No Margining
The buffered reference at V_REFOUT has the ability to source
a large amount of current. However, it can only sink a
maximum of 50μA of current. To increase the sinking
capability of this reference, connect a resistor to ground
at this pin. One may also be tempted to connect a large
capacitor to this pin to filter out the noise. However, it is
recommended that no larger than 100pF of capacitance
should be connected to this pin.
Phase-Locked Loop and Frequency Synchronization
The LTC3770 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±30% around the
center frequency f_O. The center frequency is the operating
frequency discussed in the previous section. The LTC3770
incorporates a pulse detection circuit that will detect a
18
clock on the PLLIN pin. In turn, it will turn on the phase-
locked loop function. The pulse width of the clock has
to be greater than 400ns and the amplitude of the clock
should be greater than 2V.
During the start-up phase, phase-locked loop function is
disabled. When LTC3770 is not in synchronization mode,
PLLFLTR pin voltage is set to around 1.18V. Frequency
synchronization is accomplished by changing the internal
on-time current according to the voltage on the PLLFLTR
pin.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal pulses. This type of phase detector
will not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, Δf_H,
is equal to the capture range, Δf_C:
Δf_H = Δf_C = ±0.3 f_O
The output of the phase detector is a complementary pair of
current sources charging or discharging the external filter
network on the PLLFLTR pin. A simplified block diagram
is shown in Figure 10.
If the external frequency (f_PLLIN) is greater than the oscil-
lator frequency f_O, current is sourced continuously, pulling
up the PLLFLTR pin. When the external frequency is less
than f_O, current is sunk continuously, pulling down the
PLLFLTR pin. If the external and internal frequencies are
the same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. Thus the voltage on the PLLFLTR pin is adjusted
until the phase and frequency of the external and internal
R_LP
2.4V
C_LP
PLLFLTR
PLLIN
DIGITAL
PHASE/
FREQUENCY
VCO
DETECTOR
3770 F10
Figure 10. Phase-Locked Loop Block Diagram
3770fc