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LTC3552 Datasheet, PDF (17/24 Pages) Linear Technology – Standalone Linear Li-Ion Battery Charger and Dual Synchronous Buck Converter
LTC3552
APPLICATIO S I FOR ATIO
actual overall supply performance. A feedforward capacitor,
CFF, is added to improve the high frequency response. Ca-
pacitor CFF provides phase lead by creating a high frequency
zero with the top feedback resistor, which improves the
phase margin. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
In some applications, a more severe transient can be
caused by switching loads with large (>1µF) input capaci-
tors. The discharged load input capacitors are effectively
put in parallel with COUT, causing a rapid drop in VOUT. No
regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot Swap™ controller
is designed specifically for this purpose and usually in-
corporates current limiting, short-circuit protection, and
soft-starting.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It
is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3552 circuits: 1) VCC quiescent current, 2)
switching losses, 3) I2R losses, 4) other losses.
1) The VCC current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET dri-
ver and control currents. VCC current results in a small
(< 0.1%) loss that increases with VCC, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current
results from switching the gate capacitance of the
power MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge dQ
moves from VCC to ground. The resulting dQ/dt is a
current out of VCC that is typically much larger than
the DC bias current. In continuous mode, IGATECHG =
fO(QT + QB), where QT and QB are the gate charges of
the internal top and bottom MOSFET switches. The
gate charge losses are proportional to VCC and thus
their effects will be more pronounced at higher sup-
ply voltages.
3) I2R losses are calculated from the DC resistances
of the internal switches, RSW, and external inductor,
RL. In continuous mode, the average output current
flows through inductor L, but is “chopped” between
the internal top and bottom switches. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(D) as follows:
RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
4) Other “hidden” losses such as copper trace and in-
ternal battery resistances can account for additional
efficiency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistance losses can be minimized by making sure
that CIN has adequate charge storage and very low
ESR at the switching frequency. Other losses include
diode conduction losses during dead-time and inductor
core losses generally account for less than 2% total
additional loss.
Hot Swap is a trademark of Linear Technology Corporation.
3552f
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