LTC3552 Datasheet, PDF (11/24 Pages) Linear Technology – Standalone Linear Li-Ion Battery Charger and Dual Synchronous Buck Converter

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OPERATIO
Charge Current Soft-Start
The charger includes a soft-start circuit to minimize the
inrush current at the start of a charge cycle. When a charge
cycle is initiated, the charge current ramps from zero to
full-scale current over a period of approximately 100µs.
This has the effect of minimizing the transient current load
on the power supply during start-up.
Thermal Limiting
An internal thermal feedback loop reduces the pro-
grammed charge current if the die temperature attempts
to rise above a preset value of approximately 120°C. This
feature protects the charger from excessive temperature
and allows the user to push the limits of the power handling
capability of a given circuit board without risk of damag-
ing the charger. The charge current can be set according
to typical (not worst case) ambient temperature with the
assurance that the charger will automatically reduce the
current in worst-case conditions. DFN package power
considerations are discussed further in the Applications
Information section.
Undervoltage Lockout (UVLO)
An internal undervoltage lockout circuit monitors the in-
put voltage and keeps the charger in shutdown mode
until V_IN rises above the undervoltage lockout thresh-
old. The UVLO circuit has a hysteresis of 200mV.
Also, to protect against reverse current in the power
MOSFET, the UVLO circuit keeps the charger in shutdown
mode if V_IN falls to within 30mV of the BAT voltage. If the
UVLO comparator is tripped, the charger will not come
out of shutdown mode until V_IN rises 100mV above the
BAT voltage.
Manual Shutdown
At any point in the charge cycle, the charger can be put
into shutdown mode by driving the ^⎯E^⎯N pin high. This re-
duces the battery drain current to less than 2µA and the
V_IN supply current to less than 50µA. When in shutdown
mode, the ^⎯C^⎯H^⎯R^⎯G pin is in the high impedance state. A new
charge cycle can be initiated by driving the ^⎯E^⎯N pin low. An
internal resistor pull-down on this pin forces the charger
to be enabled if the pin is allowed to float.
LTC3552
DUAL SWITCHING REGULATOR
The regulators use a current mode architecture with a
constant operating frequency of 2.25MHz. Both regula-
tors share the same clock and run in-phase. To suit a
variety of applications, the MODE/SYNC pin allows the
user to choose between low noise or high efficiency.
The output voltages are set by external resistive dividers
returned to the V_FB pins. An error amplifier compares the
divided output voltage (V_FB) with a reference voltage of
0.6V and adjusts the peak inductor current accordingly.
An undervoltage comparator will pull the ^⎯P^⎯O^⎯R output
low if V_FB is less than 91.5% of the reference voltage.
The ^⎯P^⎯O^⎯R output will go high after 262,144 clock cycles
(about 117ms in pulse-skipping mode) of achieving
regulation.
Main Regulator Control Loop
During normal operation, the top power switch (P-chan-
nel MOSFET) is turned on at the beginning of a clock
cycle when the feedback voltage is below the reference
voltage. The current into the inductor and the load in-
creases until the current limit is reached. The switch turns
off and energy stored in the inductor flows through the
bottom switch (N-channel MOSFET) into the load until the
next clock cycle. The peak inductor current is controlled
by the internally compensated I_TH voltage, which is the
output of the error amplifier. This amplifier compares
V_FB to the 0.6V reference (see Block Diagram). When
the load current increases, the V_FB voltage decreases
slightly below the reference. This decrease causes the
error amplifier to increase the I_TH voltage until the aver-
age inductor current matches the new load current. The
main control loop can be shut down by pulling the RUN
pin to ground.
Low Load Current Operation
The MODE/SYNC pin provides two modes of operation
at low currents. Both modes automatically switch from
continuous operation to the selected mode when the load
current is low. For highest efficiency at low current,
connecting the MODE/SYNC pin to V_CC makes the regu-
lator operate in Burst Mode, where the PMOS switch
operates intermittently based on load demand with a
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