LTC3870_15 Datasheet, PDF (16/22 Pages) Linear Technology – PolyPhase Step-Down Slave Controller for LTC3880/LTC3883 with Digital Power System Management

LTC3870
Applications Information
4. Is the INTV_CC bypassing capacitor connected close to
the IC, between the INTV_CC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1μF ceramic capacitor placed immediately
next to the INTV_CC and PGND pins can help improve
noise performance substantially.
5. Keep the switching nodes (SW1, SW0), top gate nodes
(TG1, TG0), and boost nodes (BOOST1, BOOST0) away
from sensitive small-signal nodes, especially from the
opposite channel’s current sensing feedback pins. All
of these nodes have very large and fast moving signals
and therefore should be kept on the “output side” of
the LTC3870 and occupy minimum PC trace area. If
DCR sensing is used, place the right resistor (Block
Diagram, “R_C”) close to the switching node.
6. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV_CC
bypassing capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a DC-
50MHz current probe to monitor the current in the inductor
while testing the circuit. Monitor the output switching node
(SW pin) to synchronize the oscilloscope to the internal
oscillator and probe the actual output voltage as well. Check
for proper performance over the operating voltage and
current range expected in the application. The frequency
of operation should be maintained over the input voltage
range down to dropout and until the output load drops below
the low current operation threshold—typically 10% of the
maximum designed current level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a sub-harmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
both controllers be turned on at the same time. A particularly
difficult region of operation is when one controller channel
is nearing its current comparator trip point when the other
channel is turning on its top MOSFET. This occurs around
50% duty cycle on either channel due to the phasing of
the internal clocks and may cause minor duty cycle jitter.
Reduce V_IN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering V_IN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output
currents or only at higher input voltages. If problems coincide
with high input voltages and low output currents, look for
capacitive coupling between the BOOST, SW, TG, and pos-
sibly BG connections and the sensitive voltage and current
pins. The capacitor placed across the current sensing pins
needs to be placed immediately adjacent to the pins of the
IC. This capacitor helps to minimize the effects of differential
noise injection due to high frequency capacitive coupling. If
problems are encountered with high current output loading
at lower input voltages, look for inductive coupling between
C_IN, Schottky and the top MOSFET components to the
sensitive current and voltage sensing traces. In addition,
investigate common ground path voltage pickup between
these components and the SGND pin of the IC.
Design Example
As a design example using master chip LTC3880 and slave
chip LTC3870 for a 4-phase high current regulator, assume
V_IN = 12V (nominal), V_IN = 15V (maximum), V_OUT = 1.0V,
I_MAX = 100A, and f = 425kHz (see Typical Applications).
The master chip LTC3880 design can be found in the
LTC3880 data sheet Design Example section.
LTC3880's SYNC pin is connected to LTC3870's SYNC
pin and LTC3870's PHASMD is connected to LTC3870’s
INTV_CC.
Slave chip LTC3870 should use the same inductor, power
MOSFET, C_IN, and C_OUT as the master chip. DCR sensing
is also used for the slave chip.
LTC3870's I_LIM pin is forced to 0V to match the master
chip's 50mV current limit. Both chips' V_IN, V_OUT, RUN,
I_TH pins are connected together. LTC3880's GPIO pins are
connected to LTC3870's FAULT pins so the slave controller
will be disabled during fault conditions.
3870fa
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