LTC3870_15 Datasheet, PDF (13/22 Pages) Linear Technology – PolyPhase Step-Down Slave Controller for LTC3880/LTC3883 with Digital Power System Management

LTC3870
Applications Information
and control power to be derived from other high efficiency
sources such as +5V or +12V rails in the system. Using
EXTV_CC can significantly reduce the IC temperature in
high V_IN applications. Tying the EXTV_CC pin to a 5V supply
reduces the junction temperature in the previous example
from 125°C to: T_J = 70°C + (34mA) (5V) (43°C/W) = 77°C.
Do not apply more than 14V to the EXTV_CC pin.
For applications where the main input power is 5V, tie
the V_IN and INTV_CC pins together and tie the combined
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
in Figure 2 to minimize the voltage drop caused by the
gate charge current. This will override the INTV_CC linear
regulator and will prevent INTV_CC from dropping too low
due to the dropout voltage. Make sure the INTV_CC voltage
is at or exceeds the R_DS(ON) test voltage for the MOSFET
which is typically 4.5V for logic-level devices.
the final arbiter is the total input current for the regulator.
If a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
Undervoltage Lockout
The LTC3870 has a precision UVLO comparator constantly
monitoring the INTV_CC voltage to ensure that an adequate
gate-drive voltage is present. It locks out the switching
action and pulls down RUN pins when INTV_CC is below
3.7V. To prevent oscillation when there is a disturbance on
the INTV_CC, the UVLO comparator has 300mV of precision
hysteresis. In multiphase operation, when LTC3870 is in
undervoltage lockout, the RUN0 and RUN1 pins are pulled
down to disable the master’s switching action.
Phase-Locked Loop and Frequency Synchronization
V_IN
LTC3870
INTV_CC
R_VIN
1Ω
5V
+ _CINTVCC
4.7µF
C_IN
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Figure 2. Setup for a 5V Input
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitor C_B, connected to the BOOST
pin, supplies the gate drive voltages for the topside MOS-
FET. Capacitor C_B in the Functional Diagram is charged
though external diode DB from INTV_CC when the SW pin
is low. When the topside MOSFET is to be turned on, the
driver places the C_B voltage across the gate source of the
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage, SW, rises to V_IN
and the BOOST pin follows. With the topside MOSFET on,
the boost voltage is above the input supply:
V_BOOST = V_IN + V_INTVCC – V_DB
The value of the boost capacitor, C_B, needs to be 100 times
that of the total input capacitance of the topside MOSFET(s).
The reverse breakdown of the external Schottky diode must
be greater than V_IN(MAX). When adjusting the gate drive level,
The LTC3870 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the internal clock to be locked
to the falling edge of an external clock signal applied to
the SYNC pin. The turn-on of channel 0/channel 1’s top
MOSFET is synchronized or out-of-phase with the falling
edge of the external clock. The phase detector is an edge
sensitive digital type that provides zero degree phase shift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics
of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal filter
network. There is a precision 10µA of current flowing out of
the FREQ pin. This allows the user to use a single resistor
to SGND to set the switching frequency when no external
clock is applied to the SYNC pin. The voltage on the FREQ
pin is equal to the resistance multiplied by 10µA current
(e.g. the voltage is 1V with a 100k resistor from the FREQ
pin to SGND). The internal switch between FREQ pin and
the integrated PLL filter network is ON, allowing the filter
network to be pre-charged to the same voltage potential
as the FREQ pin. The relationship between the voltage
on the FREQ pin and the operating frequency is shown
in Figure 3 and specified in the Electrical Characteristic
table. If an external clock is detected on the SYNC pin, the
internal switch mentioned above will turn off and isolate
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