LTC3870_15 Datasheet, PDF (14/22 Pages) Linear Technology – PolyPhase Step-Down Slave Controller for LTC3880/LTC3883 with Digital Power System Management

LTC3870
Applications Information
the influence of FREQ pin. Note that the LTC3870 can only
be synchronized to an external clock whose frequency is
within the range of the LTC3870’s internal VCO. This is
guaranteed to be between 100kHz and 1MHz. A simplified
block diagram is shown in Figure 4.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f_OSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than f_OSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
Typically, the external clock (on SYNC pin) input high
threshold is 2V, while the input low threshold is 0.4V.
Fault Protection and Responses
1400
1200
1000
800
600
400
200
0
0
0.5
1
1.5
2 2.5
FREQ PIN VOLTAGE (V)
3870 F02
Figure 3. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
EXTERNAL
OSCILLATOR
SYNC
2.4V 5V
10µA
R_SET
FREQ
DIGITAL
PHASE/ ^SYNC
FREQUENCY
DETECTOR
VCO
LTC3880/LTC3883 master controllers monitor system
voltage, current, and temperature and provide many pro-
tection features during fault conditions. LTC3870 slave
controllers do not provide as many fault monitors as master
controllers and have to respond to fault signals from the
master controller. FAULT0 and FAULT1 pins are designed
to share fault signals between masters and slaves. In a
typical parallel application, connect the FAULT pins on
LTC3870 to the master GPIO pins of the corresponding
paralleled channels and program the master GPIO as
fault sharing, so that the slave controller can respond to
all fault protections from the master. When the FAULT pin
is pulled below 1.4V, both TG and BG in the correspond-
ing channel are pulled down and external MOSFETs are
turned off. When the FAULT pin voltage is above 2V, the
corresponding channel is back to the normal operation.
During fault conditions, all internal circuits in LTC3870 are
still running so the slave controllers can immediately go
back to normal operation when the FAULT pin is released.
LTC3870 has internal thermal shutdown protection which
pulls all TG and BG pins low when the junction temperature
3870 F03
Figure 4. Phase-Locked Loop Block Diagram
is higher than 160°C. In thermal shutdown, FAULT0 and
FAULT1 pins are also pulled low. There is a 500k pull down
resistor on each FAULT pin which sets the default voltage
on Fault pins low if FAULT pins are floating.
Transient Response and Loop Stability
In a typical parallel operation, LTC3870 cooperates with
master controllers to supply more current. To achieve
balanced current sharing between master and slave, it is
recommended that each slave channel copy the design
from the master channel. Select same inductors, same
power MOSFETs, same current sensing circuit and same
output capacitors between the master channel and slave
channels. Control loop and compensation design on the
I_TH pin should start with the single phase operation of the
3870fa
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