LTC3870_15 Datasheet, PDF (15/22 Pages) Linear Technology – PolyPhase Step-Down Slave Controller for LTC3880/LTC3883 with Digital Power System Management

LTC3870
Applications Information
master controller. If the master and slave channels are
exactly the same, then the transient response and loop
stability of the multiphase design is almost the same as
the single phase operation of the master by tying the I_TH
pins together between the master and slaves. For example,
design the compensation for a single phase 1.8V/20A output
using LTC3880 with a 0.56μH inductor and 530μF output
capacitors. To extend the output to 1.8V/40A, simply parallel
one channel of LTC3870 with the same inductor and output
capacitors (total output capacitors are 1060μF) and tie the
I_TH pin of LTC3870 to the master I_TH. The loop stability
and transient responses of the two phase converter are
very similar to the single phase design without any extra
compensator on the I_TH pin of LTC3870 slave controller.
Furthermore, LTpowerCAD is provided on the LTC website
as a free download for transient and stability analysis.
To minimize the high frequency noise on the I_TH trace
between master and slave I_TH pins, a small filter capacitor
in the range of tens of pF can be placed closely at each I_TH
pin of the slave controller. This small capacitor normally
does not significantly affect the closed loop bandwidth but
increases the gain margin at high frequency.
Mode Selection and Pre-Biased Startup
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging the
output capacitors. The LTC3870 can be configured to DCM
mode for pre-biased start-up. If PGOOD signal is available
on the master controller (e.g. LTC3883), the PGOOD pin
can be connected to MODE pins of LTC3870 to ensure DCM
operation at startup and CCM operation at steady state.
Minimum On-Time Considerations
Minimum on-time t_ON(MIN) is the smallest time duration
that the LTC3870 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
t_ON(MIN) <T_SW V_OUT/V_IN
where T_SW is the switching period.
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated, but
the ripple voltage and current will increase. The minimum
on-time for the LTC3870 is approximately 90ns, with rea-
sonably good PCB layout, minimum 30% inductor current
ripple and at least 10mV ripple on the current sense signal.
The minimum on-time can be affected by PCB switch-
ing noise in the current loop. As the peak sense voltage
decreases, the minimum on-time gradually increases to
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 5. Figure 6 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in the PC layout:
1. Are the top N-channel MOSFETs M1 and M3 located within
1 cm of each other with a common drain connection
at C_IN? Do not attempt to split the input bypassing for
the two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C_INTVCC must return to the combined C_OUT (–) terminals.
The I_TH traces should be as short as possible. The path
formed by the top N-channel MOSFET, Schottky diode
and the C_IN capacitor should have short leads and PC
trace lengths. The output capacitor (–) terminals should
be connected as close as possible to the (–) terminals of
the input capacitor by placing the capacitors next to each
other and away from the Schottky loop described above.
3. Are the I_SENSE+ and I_SENSE– leads routed together with
minimum PC trace spacing? The filter capacitor between
I_SENSE+ and I_SENSE– should be as close as possible to
the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor or inductor, whichever
is used for current sensing.
3870fa
For more information www.linear.com/LTC3870
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