LTC3411_15 Datasheet, PDF (14/24 Pages) Linear Technology – 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter

LTC3411
APPLICATIONS INFORMATION
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
The I_TH external components shown in the Figure 1 circuit
will provide an adequate starting point for most applica-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1μs
to 10μs will produce output voltage and I_TH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V_OUT im-
mediately shifts by an amount equal to ΔI_LOAD • ESR, where
ESR is the effective series resistance of C_OUT. ΔI_LOAD also
begins to charge or discharge C_OUT generating a feedback
error signal used by the regulator to return V_OUT to its
steady-state value. During this recovery time, V_OUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
C_F can be added to improve the high frequency response,
as shown in Figure 5. Capacitor C_F provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V_IN drops toward V_OUT, the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
V_IN
2.5V
TO 5.5V
+
C6
C_IN
PGND
C8
PGND
R6
SV_IN
PV_IN PGOOD
SW
LTC3411
SGND
SYNC/MODE
I_TH
V_FB
SGND
C_ITH
R_C
SGND PGND SHDN/R_T
C_C
R5
PGOOD
D1 ^L1 C_F
OPTIONAL
R1
R2
R_T
SGND SGND
GND
SGND SGND
Figure 5. LTC3411 General Schematic
+
C_OUT
V_OUT
C5
PGND
PGND
3411 F05
3411fb
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