LTC3827 Datasheet, PDF (13/36 Pages) Linear Technology – Low IQ, Dual, 2-Phase Synchronous Step-Down Controller

LTC3827
OPERATION (Refer to Functional Diagram)
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3827’s controllers can
be selected using the PLLLPF pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the PLLLPF pin can be floated, tied to INTV_CC,
or tied to SGND to select 400kHz, 530kHz, or 250kHz,
respectively.
A phase-locked loop (PLL) is available on the LTC3827
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. In this
case, a series R-C should be connected between the
PLLLPF pin and SGND to serve as the PLL’s loop filter.
The LTC3827 phase detector adjusts the voltage on the
PLLLPF pin to align the turn-on of controller 1’s external
top MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external top MOSFET is
180 degrees out of phase to the rising edge of the external
clock source.
The typical capture range of the LTC3827’s phase-locked
loop is from approximately 115kHz to 800kHz, with a
guarantee over all manufacturing variations to be between
140kHz and 650kHz. In other words, the LTC3827’s PLL
is guaranteed to lock to an external clock source whose
frequency is between 140kHz and 650kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3827 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with
the LTC3827 in PolyPhase^® applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal as well as the relative phases
between the two internal controllers, as summarized in
PolyPhase is a registered trademark of Linear Technology Corporation.
Table 1. The phases are calculated relative to the zero
degrees phase being defined as the rising edge of the top
gate driver output of controller 1 (TG1).
Table 1
V_PHASMD
GND
Floating
INTV_CC
CONTROLLER 2 PHASE
180°
180°
240°
CLKOUT PHASE
60°
90°
120°
Output Overvoltage Protection
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the V_FB pin rises by more
than 10% above its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good (PGOOD1 and PGOOD2) Pins
Each PGOOD pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the corresponding V_FB pin
voltage is not within ±10% of the 0.8V reference voltage.
The PGOOD pin is also pulled low when the corresponding
RUN pin is low (shut down). When the V_FB pin voltage
is within the ±10% requirement, the MOSFET is turned
off and the pin is allowed to be pulled up by an external
resistor to a source of up to 8.5V.
Foldback Current (FOLDDIS Pin)
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the V_FB voltage is keeping up with the
TRACK/SS voltage) or when the FOLDDIS pin is pulled
high to INTV_CC.
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