LTC3827 Datasheet, PDF (12/36 Pages) Linear Technology – Low IQ, Dual, 2-Phase Synchronous Step-Down Controller

LTC3827
OPERATION (Refer to Functional Diagram)
external resistor divider from the other supply to ground
(see Applications Information section).
When the corresponding RUN pin is pulled low to disable
a controller, or when V_IN drops below its undervoltage
lockout threshold of 3.5V, the TRACK/SS pin is pulled low
by an internal MOSFET. When in undervoltage lockout,
both controllers are disabled and the external MOSFETs
are held off.
Light Load Current Operation (Burst Mode Operation,
Pulse Skipping or Continuous Conduction)
(PLLIN/MODE Pin)
The LTC3827 can be enabled to enter high efficiency Burst
Mode operation, constant frequency pulse skipping mode,
or forced continuous conduction mode at low load cur-
rents. To select Burst Mode operation, tie the PLLIN/MODE
pin to a DC voltage below 0.7V (e.g., SGND). To select
forced continuous operation, tie the PLLIN/MODE pin to
INTV_CC. To select pulse-skipping mode, tie the PLLIN/
MODE pin to a DC voltage greater than 0.9V and less than
INTV_CC – 1.2V.
When a controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-tenth of the maximum sense voltage even though the
voltage on the I_TH pin indicates a lower value. If the aver-
age inductor current is lower than the load current, the
error amplifier EA will decrease the voltage on the I_TH pin.
When the I_TH voltage drops below 0.4V, the internal sleep
signal goes high (enabling “sleep” mode) and both external
MOSFETs are turned off. The I_TH pin is then disconnected
from the output of the EA and “parked” at 0.425V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3827 draws.
If one channel is shut down and the other channel is in
sleep mode, the LTC3827 draws only 80μA of quiescent
current. If both channels are in sleep mode, the LTC3827
draws only 115μA of quiescent current. In sleep mode,
the load current is supplied by the output capacitor. As
the output voltage decreases, the EA’s output begins to
rise. When the output voltage drops enough, the I_TH pin
is reconnected to the output of the EA, the sleep signal
goes low, and the controller resumes normal operation
by turning on the top external MOSFET on the next cycle
of the internal oscillator.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus, the
controller operates in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the I_TH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than
in Burst Mode operation. However, continuous has the
advantages of lower output ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse skipping
mode or clocked by an external clock source to use the
phase-locked loop (see Frequency Selection and Phase-
Locked Loop section), the LTC3827 operates in PWM
pulse skipping mode at light loads. In this mode, constant
frequency operation is maintained down to approximately
1% of designed maximum output current. At very light
loads, the current comparator I_CMP may remain tripped for
several cycles and force the external top MOSFET to stay
off for the same number of cycles (i.e., skipping pulses).
The inductor current is not allowed to reverse (discon-
tinuous operation). This mode, like forced continuous
operation, exhibits low output ripple as well as low audio
noise and reduced RF interference as compared to Burst
Mode operation. It provides higher low current efficiency
than forced continuous mode, but not nearly as high as
Burst Mode operation.
Frequency Selection and Phase-Locked Loop (PLLLPF
and PLLIN/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
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