LTC3412A Datasheet, PDF (12/20 Pages) Linear Technology – 3A, 4MHz, Monolithic Synchronous Step-Down Regulator

LTC3412A
APPLICATIO S I FOR ATIO
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
V_OUT
=
0.8V



1+
R2 
R1
The resistive divider allows pin V_FB to sense a fraction of
the output voltage as shown in Figure 2.
V_OUT
R2
V_FB
LTC3412A
R1
SGND
3412A F02
Figure 2. Setting the Output Voltage
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than V_IN by
1V, Burst Mode operation is enabled. During Burst Mode
Operation, the voltage on the SYNC/MODE pin determines
the burst clamp level, which sets the minimum peak
inductor current, I_BURST. To select the burst clamp level,
use the graph of Minimum Peak Inductor Current vs Burst
Clamp Voltage in the Typical Performance Characteristics
section.
V_BURST is the voltage on the SYNC/MODE pin. I_BURST
can only be programmed in the range of 0A to 6A. For
values of V_BURST greater than 1V, I_BURST is set at 6A. For
values of V_BURST less than 0.4V, I_BURST is set at 0A. As
the output load current drops, the peak inductor currents
decrease to keep the output voltage in regulation. When
the output load current demands a peak inductor current
that is less than I_BURST, the burst clamp will force the peak
inductor current to remain equal to I_BURST regardless of
further reductions in the load current. Since the average
inductor current is greater than the output load current,
the voltage on the I_TH pin will decrease. When the I_TH
voltage drops to 150mV, sleep mode is enabled in which
both power MOSFETs are shut off along with most of the
circuitry to minimize power consumption. All circuitry is
turned back on and the power MOSFETs begin switching
again when the output voltage drops out of regulation.
The value for I_BURST is determined by the desired amount
of output voltage ripple. As the value of I_BURST increases,
the sleep period between pulses and the output voltage
ripple increase. The burst clamp voltage, V_BURST, can be
set by a resistor divider from the V_FB pin to the SGND pin
as shown in Figure 1.
Pulse skipping, which is a compromise between low out-
put voltage ripple and efficiency, can be implemented by
connecting pin SYNC/MODEto ground. This sets I_BURST to
0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator. The
lowest output voltage ripple is achieved while still operat-
ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3412A’s internal oscillator can be synchronized
to an external clock signal. During synchronization, the
top MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set
by the external resistor. Because slope compensation
is generated by the oscillator’s RC circuit, the external
frequency should be set 25% higher than the frequency
set by the external resistor to ensure that adequate slope
compensation is present.
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3412A as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412A in a low
quiescent current shutdown state (I_Q < 1μA).
The LTC3412A contains an internal soft-start clamp that
gradually raises the clamp on I_TH after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on I_TH after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on I_TH can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
t_SS
=
R_SS
C_SS
ln



V_IN
V_IN
– 1.8V


(SECONDS)
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12