LTC3878_15 Datasheet, PDF (11/26 Pages) Linear Technology – Fast, Wide Operating Range No RSENSE Step-Down DC/DC Controller

LTC3878
Applications Information
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
P_TOP = D_TOP •I_OUT(MAX)2 • ρ_τ(TOP) • R_DS(ON)(MAX)
( ) +V_IN2


I_OUT(MAX)
2


C_MILLER



DR_TGHIGH
V_INTVCC – V_MILLER
+
DR_TGLOW
V_MILLER



f_OSC
P_BOT = D_BOT •I_OUT(MAX)2 • ρ_τ(BOT) •R_DS(ON)(MAX)
DR_TGHIGH is pull-up driver resistance and DR_TGLOW is the
TG driver pull-down resistance. V_MILLER is the Miller ef-
fect V_GS voltage and is taken graphically from the power
MOSFET data sheet.
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate charge”
curve included on the most data sheets (Figure 2). The
curve is generated by forcing a constant input current
into the gate of a common source, current source, loaded
stage and then plotting the gate versus time. The initial
slope is the effect of the gate-to-source and gate-to-drain
capacitance. The flat portion of the curve is the result of the
Miller multiplication effect of the drain-to-gate capacitance
as the drain drops the voltage across the current source
load. The upper sloping line is due to the drain-to-gate
accumulation capacitance and the gate-to-source capaci-
tance. The Miller charge (the increase in coulombs on the
horizontal axis from a to b while the curve is flat) is speci-
fied from a given V_DS drain voltage, but can be adjusted
for different V_DS voltages by multiplying by the ratio of
the application V_DS to the curve specified V_DS values. A
way to estimate the C_MILLER term is to take the change in
gate charge from points a and b or the parameter Q_GD on
a manufacturers data sheet and divide by the specified
V_DS test voltage, V_DS(TEST).
C_MILLER
=
Q_GD
V_DS(TEST)
C_MILLER is the most important selection criteria for deter-
mining the transition loss term in the top MOSFET but is
not directly specified on MOSFET data sheets.
V_IN
MILLER EFFECT
V_GS
a
b
Q_IN
C_MILLER = (Q_B – Q_A)/V_DS
V
+
V_G–S
+
– ^VDS
3878 F02
Figure 2. Gate Charge Characteristic
Both MOSFETs have I²R power loss, and the top MOSFET
includes an additional term for transition loss, which are
highest at high input voltages. For V_IN < 20V, the high cur-
rent efficiency generally improves with larger MOSFETs,
while for V_IN > 20V, the transition losses rapidly increase
to the point that the use of a higher R_DS(ON) device with
lower C_MILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Lowering the operating fre-
quency improves efficiency by reducing MOSFET switching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.
The operating frequency of LTC3878 applications is de-
termined implicitly by the one-shot timer that controls the
on-time, t_ON, of the top MOSFET switch. The on-time is
set by the current into the I_ON pin according to:
( ) ^t_ON
=
0.7V
I_ION
10pF
Tying a resistor R_ON from V_IN to the I_ON pin yields an
on-time inversely proportional to V_IN. For a step-down
converter, this results in pseudo fixed frequency operation
as the input supply varies.
( ) ^fOP
=
0.7V
V_OUT
• R_ON
10pF
[Hz]
3878fa
11