LTC3828_15 Datasheet, PDF (10/32 Pages) Linear Technology – Dual, 2-Phase Step-Down Controller with Tracking

LTC3828
OPERATION (Refer to Functional Diagram)
Main Control Loop
The IC uses a constant frequency, current mode step-down
architecture with the two controller channels operating
180 degrees out of phase. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
comparator, I₁, resets the RS latch. The peak inductor
current at which I₁ resets the RS latch is controlled by
the voltage on the I_TH pin, which is the output of each
error amplifier EA. The V_OSENSE pin receives the voltage
feedback signal, which is compared to the internal refer-
ence voltage by the EA. When the load current increases,
it causes a slight decrease in V_OSENSE relative to the 0.8V
reference, which in turn causes the I_TH voltage to increase
until the average inductor current matches the new load
current. After the top MOSFET has turned off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by current comparator I₂,
or the beginning of the next cycle.
The top MOSFET drivers are biased from floating bootstrap
capacitor, C_B, which normally is recharged during each off
cycle through an external diode when the top MOSFET
turns off. As V_IN decreases to a voltage close to V_OUT,
the loop may enter dropout and attempt to turn on the
top MOSFET continuously. The dropout detector detects
this and forces the top MOSFET off for about 400ns every
tenth cycle to allow C_B to recharge.
The main control loop is shut down by pulling the RUN
pin low. When the RUN pin reaches 1.5V, the main control
loop is enabled. When both RUN1 and RUN2 are low,
all controller functions are shut down, including the 5V
regulator.
Low Current Operation
The FCB/PLLIN pin is a multifunction pin providing two
functions: 1) to accept external clock signal; and 2) to
select among three modes of light load operations. When
the FCB/PLLIN pin voltage is below 0.75V, the control-
ler forces continuous PWM current mode operation. In
this mode, the top and bottom MOSFETs are alternately
turned on to maintain the output voltage independent of
direction of inductor current. When the FCB/PLLIN pin is
below V_INTVCC – 0.7V but greater than 0.8V, the controller
10
enters Burst Mode operation. Burst Mode operation sets
a minimum output current level before inhibiting the top
switch and turns off the synchronous MOSFET(s) when
the inductor current goes negative. This combination of
requirements will, at low currents, force the I_TH pin below
a voltage threshold that will temporarily inhibit turn-on of
both output MOSFETs until the output voltage drops. There
is 60mV of hysteresis in the burst comparator B tied to
the I_TH pin. This hysteresis produces output signals to the
MOSFETs that turn them on for several cycles, followed by
a variable “sleep” interval depending upon the load current.
The resultant output voltage ripple is held to a very small
value by having the hysteretic comparator after the error
amplifier gain block. When the FCB/PLLIN pin voltage is
above 4.8V, the controller operates in constant frequency
mode and the synchronous MOSFET is turned off when
inductor current nears zero in each cycle.
In order to prevent erratic operation if no external con-
nections are made to the FCB/PLLIN pin, the FCB/PLLIN
pin has a 0.18μA internal current source pulling the pin
high.
The following table summarizes the possible states avail-
able on the FCB/PLLIN pin:
Table 1
FCB/PLLIN PIN
0V to 0.75V
0.85V < V_FCB/PLLIN < 4.3V
or Open
>4.8V
CONDITION
Forced Continuous Both Controllers
(Current Reversal Allowed—
Burst Inhibited)
Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
Besides providing a logic input to select light load op-
eration mode, the FCB/PLLIN pin acts as the input for
external clock synchronization. Upon detecting the pres-
ence of an external clock signal, channel 1 will lock on to
this external clock and this will be followed by channel 2
(see Frequency Synchronization section). The LTC3828
defaults to forced continuous mode when sychronized to
an external clock.
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