LTC3618 Datasheet, PDF (9/24 Pages) Linear Integrated Systems – Dual 4MHz, 3A Synchronous Buck Converter for DDR Termination

LTC3618
PIN FUNCTIONS (FE/UF)
MODE/SYNC (Pin 24/Pin 3): Mode Selection.
1. Tying the MODE pin to SV_IN or SGND enables pulse-
skipping mode or forced continuous mode respectively
for V_DDQ only. The default operation mode for V_TT is
forced continuous mode. The input to the MODE/SYNC
pin should be a digital signal.
2. When a clock signal is applied to this pin, the switching
frequency synchronizes to this clock signal and forced
continuous mode is selected for V_DDQ.
PGND (Exposed Pad Pin 25/ Exposed Pad Pin 25): Power
Ground. The exposed pad connects to the sources of the
power N-channel MOSFETs. The PGND pin is common
for both channels. The exposed pad must be soldered
to the PCB for electrical connection and rated thermal
performance. Refer to the Operation and Applications
Information sections for more information.
FUNCTIONAL BLOCK DIAGRAM
PGOOD1
FB1
V_REF
IDEAL
DIODE
MODE/SYNC
TRACK/SS1
DELAY
ERROR
–
AMPLIFIER
+
SOFT-START
PGOOD
WINDOW-
COMPARATOR
ITH1
V_DDQ
INTERNAL/
EXTERNAL
COMPENSATION
ITH-VOLTAGE
LIMIT
SLOPE
COMPENSATION
PMOS
CURRENT
COMPARATOR
PMOS
CURRENT SENSE
PV_IN1
CONTROLLER LOGIC
SW1
GATE DRIVER
RUN1
RUN2
RT
PHASE
SV_IN
SGND
VTTR
UNDERVOLTAGE
LOCKOUT
OVERVOLTAGE
LOCKOUT
CLK1
OR
PLL
OSCILLATOR
AND PHASE
SELECTOR
CLK2
SHUTDOWN
REVERSE
CURRENT
COMPARATOR
PGOOD2
FB2
–
ERROR
AMPLIFIER
+
NMOS
CURRENT SENSE
0A
ITH2
VDDQIN
R
R
PGND
DUPLICATE FOR V_TT
PV_IN2
SW2
3618 FD
3618fb
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