LTC3618 Datasheet, PDF (15/24 Pages) Linear Integrated Systems – Dual 4MHz, 3A Synchronous Buck Converter for DDR Termination

LTC3618
APPLICATIONS INFORMATION
This formula has a maximum at V_IN = 2V_OUT, where I_RMS =
I_OUT/2. This simple worst-case condition is commonly used
for design because even significant deviations do not offer
much relief. Note that ripple current ratings from capacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design.
Output Capacitor C_OUT Selection
The selection of C_OUT is typically driven by the required
ESR to minimize voltage ripple and load step transients
(low-ESR ceramic capacitors are discussed in the next
section). Typically, once the ESR requirement is satisfied,
the capacitance is adequate for filtering. The output ripple
ΔV_OUT is determined by:
V_OUT


I_L
•

ESR +

8
•
1
f_SW •
C_OUT



where f_SW = operating frequency, C_OUT = output capacitance
and ΔI_L = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔI_L increases
with input voltage.
In surface mount applications, multiple capacitors may
be paralleled to meet the capacitance, ESR or RMS cur-
rent handling requirement of the application. Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
Tantalum capacitors have the highest capacitance density,
but can have higher ESR and must be surge tested for
use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can often
be used in extremely cost-sensitive applications provided
that consideration is given to ripple current ratings and
long term reliability.
Ceramic Input and Output Capacitors
Ceramic capacitors have the lowest ESR and can be cost
effective, but also have the lowest capacitance density,
high voltage and temperature coefficients, and exhibit
audible piezoelectric effects. In addition, the high-Q of
ceramic capacitors along with trace inductance can lead
to significant ringing.
Ceramic capacitors are tempting for switching regulator
use because of their very low ESR. Great care must be
taken when using only ceramic input and output capacitors.
Ceramic caps are prone to temperature effects which re-
quire the designer to check loop stability over the operating
temperature range. To minimize their large temperature
and voltage coefficients, only X5R or X7R ceramic capaci-
tors should be used.
When a ceramic capacitor is used at the input, and the
power is being supplied through long wires, such as from
a wall adapter, a load step at the output can induce ringing
at the V_IN pin. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, the ringing
at the input can be large enough to damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation com-
ponents and the output capacitor size. Typically, three to
four cycles are required to respond to a load step, but
only in the first cycle does the output drop linearly. The
output droop, V_DROOP, is usually about two to three times
the linear drop of the first cycle. Thus, a good place to
start is with the output capacitor size of approximately:
C_OUT
≈
2.5 • ΔI_OUT
f_SW • V_DROOP
More capacitance may be required depending on the duty
cycle and load step requirements. In most applications, the
input capacitor is merely required to supply high frequency
bypassing, since the impedance to the supply is very low.
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