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LTC3589_12 Datasheet, PDF (42/50 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C
LTC3589/LTC3589-1/
LTC3589-2
OPERATION
LDO2 and step-down switching regulators 1 to 3 each have
a pair of control bits in the voltage change control register
VCCR. The reference select bit selects which of two 5-bit
words are used as inputs to the regulators feedback refer-
ence DAC inputs. The slew GO bit initiates a DAC slew to
the voltage selected by the reference select bit. When the
slew is complete, the slew GO bits are reset LOW.
Accessing the CLIRQ command register will clear the IRQ
pin and will let the IRQ pin to release HIGH. The pin is
cleared when the LTC3589 acknowledges the sub address.
Data written to the CLIRQ command register is ignored.
There are eight command registers that are used to store
the 5-bit dynamic target voltage input to the feedback
reference slewing DACs – B1DTV1, B1DTV2, B2DTV1,
B2DTV2, B3DTV1, B3DTV2, L2DTV1 and L2DTV2. The
registers ending with V2 use bits 4 through 0 to store
the V2 feedback reference voltage for the regulators. The
regulators input reference voltage is set to V2 by setting
the reference select bits HIGH in VCCR and writing to the
go bits in VCCR. The V2 voltage is also selected whenever
the VSTB pin is driven HIGH. The registers ending with
V1 use bits 4 through 0 to store the V1 feedback voltage
reference for the regulators. The regulators input refer-
ence voltage is set to V1 voltage by setting the reference
select bits LOW in command register VCCR. Whenever
a new dynamic target voltage is set, either by changing
the 5-bit value or by changing the reference select bits in
VCCR, the go bits in VCCR must be written to initiate the
dynamic voltage slew. When bit 5 in B1DTV1, B2DTV1,
B3DTV1, and L2DTV1 is LOW the PGOOD pin pulls LOW
during a dynamic voltage slew. Bits 7 and 6 in B1DTV1
set the switch DV/DT rate for all the step-down switch-
ing regulators. Bit 5 in registers B1DTV2, B2DTV2 and
B3DTV2 selects the switching frequency of step-down
switching regulators 1, 2 and 3. Writing the bit LOW sets
the switching frequency to 2.25MHz. Writing the bit HIGH
sets the switching frequency to 1.125MHz.
The dynamic slew rates of the four feedback reference
DACs are independently set using bits in voltage ramp
rate command register (VRRCR). The rate shown is the
slew of the DAC output as it slews up or down to its target
value. The slew rate of the output voltage is scaled by the
gain of the resistor divider network that sets the regulator
output voltage. For example, a regulator set to an output
voltage of 1.2V when the dynamic target voltage reference
is 0.75V has a gain of 1.6. Slewing the regulator output
from 1.2V to 1V requires slewing the DAC output down
125mV from 750mV to 625mV. With a VRRCR slew rate
setting of 01 the slew time of the regulator output is 71μs.
THERMAL CONSIDERATIONS AND BOARD LAYOUT
Printed Circuit Board Power Dissipation
In order to ensure optimal performance and the ability
to deliver maximum output power to any regulator, it is
critical that the exposed ground pad on the backside of
the LTC3589 package be soldered to a ground plane on
the board. The exposed pad is the only GND connection
for the LTC3589. Correctly soldered to a 2500mm2 ground
plane on a double sided 1oz copper board the LTC3589
has a thermal resistance (θJA) of approximately 34°C/W.
Failure to make good thermal contact between the exposed
pad on the backside of the package and an adequately
sized ground plane will result in thermal resistances far
greater than 34°C/W.
To ensure the junction temperature of the LTC3589 die
does not exceed the maximum rated limit and to prevent
overtemperature faults, the power output of the LTC3589
must be managed by the application. The total power
dissipation in the LTC3589 is approximated by summing
the power dissipation in each of the switching regulators
and the LDO regulators.
The power dissipation in a switching regulator is esti-
mated by:
PD(SWX )
= (VOUTX
• IOUTX)•
100 – Eff
100
Where VOUTX is the programmed output voltage, IOUTX
is the load current and Eff is the % efficiency that can
be measured or looked up in an efficiency table for the
programmed output voltage.
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