LTC3589_12 Datasheet, PDF (36/50 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589/LTC3589-1/
LTC3589-2
OPERATION
I²C OPERATION
I²C Interface
The LTC3589 communicates with a bus master using the
standard I²C 2-wire interface. The two bus lines, SDA and
SCL, must be HIGH when the bus is not in use. External
pull-up resistors or current sources, such as the LTC1694
SMBus accelerator, are required on these lines. The
LTC3589 is both a slave receiver and slave transmitter. The
I²C control signals, SDA and SCL are scaled internally to
the DV_DD supply. DV_DD should be connected to the same
power supply as the bus pull-up resistors.
The I²C port has an undervoltage lockout on the DV_DD
pin. When DV_DD is below approximately 1V, the I²C serial
port is reset to power-on states and registers are set to
default values.
I²C Bus Speed
The I²C port operates at speeds up to 400kHz. It has
built-in timing delays to ensure correct operation when
addressed from an I²C compliant master device. It also
contains input filters designed to suppress glitches should
the bus become corrupted.
I²C START and STOP Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3589, the master may transmit a STOP condition that
commands the LTC3589 to act upon its new command
set. A STOP condition is sent by the master by transition-
ing SDA from LOW to HIGH while SCL is HIGH. The bus
it then free for communication with another I²C device.
I²C Byte Format
Each byte sent to or received from the LTC3589 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3589
most significant bit (MSB) first.
I²C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3589 is written to,
it acknowledges its write address and subsequent register
address and data bytes. When reading from the LTC3589,
it acknowledges its read address and 8-bit status byte.
An acknowledge pulse (active LOW) generated by the
LTC3589 lets the master know that the latest byte of
information was transferred. The master generates the
clock cycle and releases the SDA line (HIGH) during the
acknowledge clock cycle. The LTC3589 pulls down the SDA
line during the write acknowledge clock pulse so that it is
a stable LOW during the HIGH period of this clock pulse.
I²C Slave Address
The LTC3589 responds to factory programmed read and
write addresses. The write address is 0x68. The read ad-
dress is 0x69. The least significant bit of the address byte,
known as the read/write bit, is 0 when writing data to the
LTC3589 and 1 when reading from it.
ADDRESS
0 1 1 0 1 0 0 WR
SUB ADDRESS
S7 S6 S5 S4 S3 S2 S1 S0
ADDRESS
0 1 1 0 1 0 0 RD
DATA
R7 R6 R5 R4 R3 R2 R1 R0
START
SDA
0 1 1 0 1 0 0 0 ACK
START
ACK
0 1 1 0 1 0 0 1 ACK
STOP
ACK
SCL
123456789123456789
123456789123456789
3589 F20
Figure 20. LTC3589 I²C Serial Port Read Pattern
3589fe
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