LTC3589_12 Datasheet, PDF (33/50 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589/LTC3589-1/
LTC3589-2
OPERATION
RSTO Pin Function
The RSTO (reset output) pin is an open-drain output for use
as a power-on reset signal. It is pulled LOW at initial power
until LDO1 is within 8% of its target and the initial one second
start-up timer is finished. RSTO remains HIGH during normal
operation and will be pulled low if LDO1 loses regulation for
more than 25μs or a pushbutton hard reset is initiated. RSTO
is released high 14ms after LDO1 returns to regulation.
Figure 13 shows a initial power-up for the RSTO pin. If V_IN
is not above its undervoltage thresholds at the end of the 1
second start-up time, the IRQ pin will be pulled LOW and an
undervoltage bit will be set in the IRQSTAT status register.
V_IN ^2.7V
–8%
LDO1
25μs
RSTO
1 SEC
14ms
INITIAL POWER-UP
LDO1 UNDERVOLTAGE
LTC3589
V_IN
–8%
LDO1
25μs
RSTO
14ms
14ms
INITIAL POWER-UP
LDO1 UNDERVOLTAGE
LTC3589-1/LTC3589-2
3589 F13
Figure 13. Initial Power-Up and LDO1 Undervoltage RSTO Timing
PGOOD Pin and PGSTAT Status Register Function
Each LTC3589 regulator has an internal power good out-
put that is active whenever the regulators feedback pin is
closer than 7% (typical) from its input reference voltage.
If any of the internal power good signals indicate a low
voltage for longer than 25μs (typical), the PGOOD pin is
pulled LOW and the appropriate bit in the PGSTAT status
register (Table 15) is set.
Table 15. PGSTAT Read-Only Register Bit Definitions
PGSTAT[BIT] VALUE SETTING
0
0 LDO1_STBY Output Low
1 ^{LDO1_STBY Output Good}
1
0 Step-Down Switching Regulator 1 Output Low
1 ^{Step-Down Switching Regulator 1 Output Good}
2
0 Step-Down Switching Regulator 2 Output Low
1 ^{Step-Down Switching Regulator 2 Output Good}
3
0 Step-Down Switching Regulator 3 Output Low
1 ^{Step-Down Switching Regulator 3 Output Good}
4
0 Buck-Boost Regulator 4 Output Low
1 ^{Buck-Boost Regulator 4 Output Good}
5
0 LDO2 Output Low
1 ^{LDO2 Output Good}
6
0 LDO3 Output Low
1 ^{LDO3 Output Good}
7
0 LDO4 Output Low
1 ^{LDO4 Output Good}
Figure 14 shows the PGOOD pin and PGSTAT status reg-
ister timing. When no regulator is enabled, the PGOOD
pin is pulled LOW and PGSTAT bits are LOW. PGOOD and
the PGSTAT bits are HIGH 250μs after the last enabled
regulator is within 7% of its target.
WAKE
WAKE HIGH AFTER 1sec
IF PWR_ON HIGH
1sec
ENx
200μs
V_OUTx
250μs
PGOOD
IRQ
ENABLE
25μs
25μs
250μs
DISABLED IF
WAKE LOW
250μs
14ms
UNDERVOLTAGE
EXTENDED
UNDERVOLTAGE
(FAULT)
DISABLE
3589 F14
Figure 14. PGOOD Pin and PGSTAT Status Register Timing
3589fe
33