LTC3839 Datasheet, PDF (41/50 Pages) Linear Technology – Fast, Accurate, 2-Phase, Single-Output Step-Down DC/DC Controller

LTC3839
APPLICATIONS INFORMATION
these pins. If the IC can be placed on the bottom side
of a multilayer board, use ground planes to isolate from
the major power components on the top side of the
board, and prevent noise coupling to noise sensitive
components on the bottom side.
• Place the resistor feedback divider R_FB1, R_FB2 close to
V_OUTSENSE1+ and V_{OUTSENSE1–} pins, so that the feed-
back voltage tapped from the resistor divider will not
be disturbed by noise sources. Route remote sense
PCB traces (use a pair of wires closely together for
differential sensing) directly to the terminals of output
capacitors for best output regulation.
• Place decoupling capacitors C_ITH2 next to the ITH and
SGND pins with short, direct trace connections.
• Use sufficient isolation when routing a clock signal into
the MODE/PLLIN pin or out of the CLKOUT pin, so that
the clock does not couple into sensitive pins.
• Place the ceramic decoupling capacitor C_INTVCC between
the INTV_CC pin and SGND and as close as possible to
the IC.
• Place the ceramic decoupling capacitor C_DRVCC close
to the IC, between the combined DRV_CC1,2 pins and
PGND.
• Filter the V_IN input to the IC with an RC filter. Place the
filter capacitor close to the V_IN pin.
• If vias have to be used, use immediate vias to connect
components to the SGND and PGND planes of the IC.
Use multiple large vias for power components.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to DC rails only,
e.g., PGND.
PCB Layout Debugging
Only after each controller is checked for its individual
performance should both controllers be turned on at the
same time. It is helpful to use a current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator output CLKOUT, or
external clock if used. Probe the actual output voltage as
well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range. The phase should be maintained
from cycle to cycle in a well designed, low noise PCB
implementation. Variation in the phase of SW node pulse
can suggest noise pickup at the current or voltage sensing
inputs or inadequate loop compensation. Overcompensa-
tion of the loop can be used to tame a poor PCB layout if
regulator bandwidth optimization is not required.
Pay special attention to the region of operation when one
controller channel is turning on (right after its current
comparator trip point) while the other channel is turning
off its top MOSFET at the end of its on-time. This may
cause minor phase-lock jitter at either channel due to
noise coupling.
Reduce V_IN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering V_IN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins.
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