LTC3839 Datasheet, PDF (34/50 Pages) Linear Technology – Fast, Accurate, 2-Phase, Single-Output Step-Down DC/DC Controller

LTC3839
APPLICATIONS INFORMATION
The DTR comparator output is overridden by reverse
inductor current detection (I_REV) and overvoltage (OV)
condition. This means BG will be turned off when SENSE⁺
is higher than SENSE^– (i.e., inductor current is positive),
as long as the OV condition is not present. When inductor
current drops to zero and starts to reverse, BG will turn
back on in forced continuous mode (e.g., the MODE/
PLLIN pin tied to INTV_CC, or an input clock is present),
even if DTR is still below half INTV_CC. This is to allow the
inductor current to go negative to quickly pull down the
V_OUT overshoot. Of course, if the MODE/PLLIN pin is set
to discontinuous mode (i.e., tied to SGND), BG will stay
off as inductor current reverse, as it would with the DTR
feature disabled.
Also, if V_OUT gets higher than the OV window (7.5% typical),
the DTR function is defeated and BG will turn on regard-
less. Therefore, in order for the DTR feature to reduce V_OUT
overshoot effectively, sufficient output capacitance needs
to be used in the application so that OV is not triggered.
This is best to be tested experimentally with a load step
desired to have its overshoot suppressed.
This detect transient feature significantly reduces the
overshoot peak voltage, as well as time to recover (see
Typical Performance Characteristics).
Note that it is expected that this DTR feature will cause
additional loss on the bottom MOSFET, due to its body
diode conduction. The bottom MOSFET temperature may
be higher with a load of frequent and large load steps.
This is an important design consideration. An experiment
shows a 20°C increase when a continuous 100% to 50%
load step pulse train with 50% duty cycle and 100kHz
frequency is applied to the output.
If not needed, this DTR feature can be disabled by tying
the DTR pin to INTV_CC, or simply leave the DTR pin open
so that an internal 2.5μA current source will pull itself up
to INTV_CC.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
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produce the most improvement. Percentage efficiency
can be expressed as:
%Efficiency = 100% – (L1% + L2% + L3% + ...)
where L1%, L2%, etc. are the individual losses as a per-
centage of input power. Although all dissipative elements
in the circuit produce power losses, several main sources
usually account for most of the losses in LTC3839 circuits:
1. I²R loss. These arise from the DC resistances of the
MOSFETs, inductor, current sense resistor and is the ma-
jority of power loss at high output currents. In continu-
ous mode the average output current flows though the
inductor L, but is chopped between the top and bottom
MOSFETs. If the two MOSFETs have approximately the
same R_DS(ON), then the resistance of one MOSFET can
simply be summed with the inductor’s DC resistances
(DCR) and the board traces to obtain the I²R loss. For
example, if each R_DS(ON) = 8mΩ, R_L = 5mΩ, and R_SENSE
= 2mΩ the loss will range from 15mW to 1.5W as the
output current varies from 1A to 10A. This results in loss
from 0.3% to 3% a 5V output, or 1% to 10% for a 1.5V
output. Efficiency varies as the inverse square of V_OUT
for the same external components and output power
level. The combined effects of lower output voltages
and higher currents load demands greater importance
of this loss term in the switching regulator system.
2. Transition loss. This loss mostly arises from the brief
amount of time the top MOSFET spends in the satura-
tion (Miller) region during switch node transitions. It
depends upon the input voltage, load current, driver
strength and MOSFET capacitance, among other fac-
tors, and can be significant at higher input voltages or
higher switching frequencies.
3. DRV_CC current. This is the sum of the MOSFET driver
and INTV_CC control currents. The MOSFET driver cur-
rents result from switching the gate capacitance of the
power MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge dQ
moves from DRV_CC to ground. The resulting dQ/dt is a
current out of DRV_CC that is typically much larger than
the controller I_Q current. In continuous mode,
I_GATECHG = f • (Qg_(TOP) + Qg_(BOT)),
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