2096E_1 Datasheet, PDF (9/11 Pages) Lattice Semiconductor – In-System Programmable SuperFAST™ High Density PLD

Specifications ispLSI 2096E
Pin Description
NAME
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
PQFP & TQFP PIN NUMBERS
DESCRIPTION
21, 22, 23, 24, 25,
27, 28, 29, 30, 31,
34, 35, 36, 37, 38,
40, 41, 42, 43, 44,
52, 53, 54, 55, 56,
58, 59, 60, 61, 62,
66, 67, 68, 69, 70,
72, 73, 74, 75, 76,
85, 86, 87, 88, 89,
91, 92, 93, 94, 95,
98, 99, 100, 101, 102,
104, 105, 106, 107, 108,
117, 118, 119, 120, 121,
123, 124, 125, 126, 127,
2, 3,
4,
5,
6,
8, 9, 10, 11, 12,
26 Input/Output Pins - These are the general purpose I/O pins used by the
32 logic array.
39
45
57
63
71
77
90
96
103
109
122
128
7
13
GOE 0, GOE 1
IN 2, IN 4, IN 5
BSCAN
TDI/IN 0¹
64, 114
51, 84, 110
18
20
TMS/IN 1¹
46
TDO¹
50
TCK/IN 3¹
78
Global Output Enables input pins.
Dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The TMS, TDI, TDO and
TCK options become active.
Input - This pin performs two functions. When BSCAN is logic low, it
functions as an input pin to load programming data into the device.
TDI/IN0 also is used as one of the two control pins for the isp state
machine. When BSCAN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When BSCAN is logic low, it
functions as a pin to control the operation of the isp state machine.
When BSCAN is high, it functions as a dedicated input pin.
Output - When BSCAN is logic low, it functions as an output pin to read
serial shift register data.
Input - This pin performs two functions. When BSCAN is logic low, it
functions as a clock pin for the Serial Shift Register. When BSCAN is
high, it functions as a dedicated input pin.
RESET
Y0, Y1, Y2
19
15 83, 80
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
GND
1, 17, 33, 49, 65, 81, Ground (GND)
97, 112, 115, 116
VCC
16, 48, 82, 113
V_CC
VCCIO
14, 47, 79, 111
Supply voltage for output drivers, 5V or 3.3V. All VCCIO pins must be
connected to the same voltage level
1. Pins have dual function capability.
Table 2-0002/2096E
9